i.MX7 PCIe clock requirements

ulrichschmidt — Fri, 10 Feb 2017 07:07:01 GMT

Dear NXP i.MX Community,

in order pass the PCIe Gen2 compliance test for i.MX6, NXP recommends an external clock.

What about the i.MX7? Does it share the same PCIe IP? Will the internal be sufficient and what is NXP recommending?

„PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip can't pass PCIe Gen2 compliance test. Recommend using external PCIe 2.0/3.0 clock generator with 2 HCSL outputs solution. One clock channel connect to i.MX6 as a reference input, please click Ref14 for reference circuit. Another clock channel should connect to PCIe connector, please contact generator vendor for detailed design guide.“

Best regards,

Uli

Re: i.MX7 PCIe clock requirements

Yuri — Mon, 13 Feb 2017 03:47:56 GMT

Hello,

From Table 11 (PCIE recommendations) of "Hardware Development Guide for i.MX7Dual " :

"i.MX differential clock is not compliance with PCIe standard. NXP recommends including an external clock
source that meets the PCIe jitter specification untils the i.MX 7DS PCIe jitter compliance can be assessed."

http://www.nxp.com/assets/documents/data/en/user-guides/IMX7DSHDG.pdf

Regards,

Yuri.

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i.MX7 PCIe clock requirements

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