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    <title>i.MX ProcessorsのトピックRe: Question, i.MX6SX eMMC boot</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620583#M94074</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/weidong.sun"&gt;weidong.sun&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have asked the customer about&amp;nbsp;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;boot_cfg1,&amp;nbsp;&lt;SPAN&gt;boot_cfg2 setting.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;&lt;SPAN&gt;Please wait for a while.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 30 Mar 2017 07:15:20 GMT</pubDate>
    <dc:creator>SLICE</dc:creator>
    <dc:date>2017-03-30T07:15:20Z</dc:date>
    <item>
      <title>Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620569#M94060</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about eMMC BOOT of i.MX6SX.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;My customer is trying to boot-up i.MX6SX from eMMC.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;And they saw that boot cannot be done in the following case.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;- LCD1_DATA04(SRC_BOOT_CFG04)=H, LCD1_DATA15(SRC_BOOT_CFG15)=H&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;For the other settings such as below, the boot from eMMC can be done.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;- LCD1_DATA04(SRC_BOOT_CFG04)=L, LCD1_DATA15(SRC_BOOT_CFG15)=L&lt;/P&gt;&lt;P&gt;- LCD1_DATA04(SRC_BOOT_CFG04)=L, LCD1_DATA15(SRC_BOOT_CFG15)=H&lt;/P&gt;&lt;P&gt;- LCD1_DATA04(SRC_BOOT_CFG04)=H, LCD1_DATA15(SRC_BOOT_CFG15)=L&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;They are using eMMC 4.41 compliant chip, and they believe that FastBoot mode and DDR mode can be enabled simultaneously for i.MX6SX eMMC boot.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Is it true?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If yes, please let me know what they should do to achieve enabling both of FastBoot mode and DDR mode.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 06 Mar 2017 02:53:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620569#M94060</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-03-06T02:53:39Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620570#M94061</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A _jive_internal="true" data-content-finding="Community" data-userid="26074" data-username="SLICE" href="https://community.nxp.com/people/SLICE"&gt;Masamichi&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;gt;&amp;gt;i&lt;SPAN&gt;s it true?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If yes, please let me know what they should do to achieve enabling both of FastBoot mode and DDR mode.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Yes, FastBoot and DDR mode can be used simultaneously. But these 2 modes must be supported by eMMC device.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;(Weidong)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 06 Mar 2017 03:36:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620570#M94061</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2017-03-06T03:36:41Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620571#M94062</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Weidong,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your comment.&lt;/P&gt;&lt;P&gt;The customer uses eMMC 4.41 compliant device, so the eMMC chip supports both of FastMode and DDR mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 06 Mar 2017 03:48:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620571#M94062</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-03-06T03:48:21Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620572#M94063</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Weidong,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;I am still waiting for you!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;The customer uses&amp;nbsp;&lt;SPAN&gt;eMMC 4.41 compliant device,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;So could you please give advice to achieve eMMC boot with FastBoot and DDR mode&amp;nbsp;&lt;SPAN&gt;simultaneously?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 Mar 2017 07:45:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620572#M94063</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-03-13T07:45:43Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620573#M94064</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am still waiting for you!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Mar 2017 13:23:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620573#M94064</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-03-16T13:23:10Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620574#M94065</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A _jive_internal="true" data-content-finding="Community" data-userid="26074" data-username="SLICE" href="https://community.nxp.com/people/SLICE"&gt;Masamichi&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Sorry for my late reply!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; I checked errata for i.MX6SX( see document "IMX6SXCE.pdf"), There are no errors clarified on Fast boot with DDR mode in it, so Fast boot with DDR mode should be supported by i.MX6SX.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; I configured boot selection according to i.MX6SX EVK board, see following, please!&lt;/P&gt;&lt;P&gt;---------------------------------------------------------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;BOOT_CFG1[7:6] = 01 &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt; color: red;"&gt;LCD1_DATA7=0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD1_DATA6=1&lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; boot from uSHDC&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;BOOT_CFG1[5] = 1&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt; color: red;"&gt;LCD1_DATA5 = 1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt; color: black;"&gt;MMC protocal&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;BOOT_CFG1[4] = 1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt; color: red;"&gt;LCD1_DATA4 = 1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;STRONG style="color: #0070c0; font-size: 12.0pt;"&gt;Fast boot mode&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;BOOT_CFG1[3:2]=x0&amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt; color: red;"&gt;LCD1_DATA3 = x&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD1_DATA2 = 0 &amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;STRONG style="color: #0070c0; font-size: 12.0pt;"&gt;Fast boot ACK enable&lt;/STRONG&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;BOOT_CFG1[1] = 1&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt; color: red;"&gt;LCD1_DATA1 = 1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;eMMC reset enabled via the SD_RST pad&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;BOOT_CFG1[0] = 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt; color: red;"&gt;LCD1_DATA0 = 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;Through the SD pad&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;BOOT_CFG2[7:5] = 110&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 10.0pt; color: red;"&gt;LCD1_DATA15=1 &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD1_DATA14=1 &amp;nbsp;&amp;nbsp;&amp;nbsp;LCD1_DATA13=0&lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt; color: red;"&gt;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;STRONG style="color: #0070c0; font-size: 12.0pt;"&gt;8bit DDR mode&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;BOOT_CFG2[4:3] =11&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt; color: red;"&gt;LCD1_DATA12 = 1&amp;nbsp;&amp;nbsp; LCD1_DATA11=1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt;"&gt; Boot from uSDHC-4 port&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;BOOT_CFG2[2] = 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style="color: red;"&gt;LCD1_DATA10 = 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;BOOT cpu /ddr Frequecy 792/400 MHz&lt;/P&gt;&lt;P&gt;------------------------------------------------------------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;In additon, see Table 8-18. MMC and eMMC boot details (continued) of reference manual.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_4.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/16552i1248AEA30779B540/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_4.png" alt="pastedImage_4.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;In the list, Fast boot and DDR mode are described clearly!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please let customer try above! If there still exsit issues, I will confirm it with i.MX Expert team!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a nice day!&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Weidong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 20 Mar 2017 04:00:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620574#M94065</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2017-03-20T04:00:52Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620575#M94066</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN&gt;Hello Weidong,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks for your reply.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;On the customer’s lab, they saw boot failed when they set the BOOT_CFGxx as below on the SABRE board.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- LCD1_DATA04(SRC_BOOT_CFG04)=H, LCD1_DATA15(SRC_BOOT_CFG15)=H&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In my understanding, one should set BOOT_CFG2[7:5] as below for DDR mode of eMMC.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;BOOT_CFG2[7:5]=101: for 4bit DDR&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;BOOT_CFG2[7:5]=110: for 8bit DDR&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Correct?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Mar 2017 02:47:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620575#M94066</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2017-03-21T02:47:28Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620576#M94067</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Weidong,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am still waiting for your RE.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Mar 2017 01:13:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620576#M94067</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-03-27T01:13:28Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620577#M94068</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Weidong,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In my customer's understanding, it is possible for i.MX6SX to boot from eMMC with FastBoot and DDR mode simultaneously by setting BOOT_CFG1[4] =1 and BOOT_CFG2[7:5]=110(or 101).&lt;/P&gt;&lt;P&gt;Is it true?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Mar 2017 04:52:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620577#M94068</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-03-27T04:52:57Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620578#M94069</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/weidong.sun"&gt;weidong.sun&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;could you please follow-up to this question.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Mar 2017 01:59:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620578#M94069</guid>
      <dc:creator>b50231katsuhiro</dc:creator>
      <dc:date>2017-03-30T01:59:24Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620579#M94070</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN class=""&gt;&lt;A _jive_internal="true" class="" data-content-finding="Community" data-userid="26074" data-username="SLICE" href="https://community.nxp.com/people/SLICE"&gt;Masamichi&lt;/A&gt;&lt;/SPAN&gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I discussed the question with FAE and AE team, Fast boot and 8-BIT DDR mode are independent respectively!&lt;/P&gt;&lt;P&gt;I have asked my colleague Jimmy Chan to help to do test on i.MX6SX board for your question, so let us wait for result!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Weidong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Mar 2017 02:08:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620579#M94070</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2017-03-30T02:08:44Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620580#M94071</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/wigros.sun"&gt;wigros.sun&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks a lot for your support!&lt;/P&gt;&lt;P&gt;I will wait.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Mar 2017 02:14:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620580#M94071</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-03-30T02:14:03Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620581#M94072</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;could you show me all the boot_cfg1[0:7], bootcfg_2[0-7] setting?&lt;/P&gt;&lt;P&gt;thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Mar 2017 06:40:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620581#M94072</guid>
      <dc:creator>jimmychan</dc:creator>
      <dc:date>2017-03-30T06:40:20Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620582#M94073</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN class=""&gt;Hello &lt;A _jive_internal="true" class="" data-content-finding="Community" data-userid="26074" data-username="SLICE" href="https://community.nxp.com/people/SLICE"&gt;Masamichi&lt;/A&gt;,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; I found there is no eMMC Flash on i.mx6sx evk board, it is DNP status. So we have no way to do the test. We will submit the issue to i.MX Expert team.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; So I have to say sorry for it, we will have to wait for i.MX Expert team's reply!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;Have a nice day!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;Weidong&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Mar 2017 06:51:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620582#M94073</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2017-03-30T06:51:00Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620583#M94074</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/weidong.sun"&gt;weidong.sun&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have asked the customer about&amp;nbsp;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;boot_cfg1,&amp;nbsp;&lt;SPAN&gt;boot_cfg2 setting.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;&lt;SPAN&gt;Please wait for a while.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Mar 2017 07:15:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620583#M94074</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-03-30T07:15:20Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620584#M94075</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/weidong.sun"&gt;weidong.sun&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The settings are as below.&lt;/P&gt;&lt;P&gt;boot_cfg1[7:0] = b'01110000&lt;/P&gt;&lt;P&gt;boot_cfg2[7:0] = b'11010000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Apr 2017 07:42:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620584#M94075</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-04-03T07:42:53Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620585#M94076</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/jimmychan"&gt;jimmychan&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I posted the settings of&amp;nbsp;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;boot_cfg1[0:7], bootcfg_2[0-7] to the Community.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;&lt;A href="https://community.nxp.com/thread/446176"&gt;https://community.nxp.com/thread/446176&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Apr 2017 07:46:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620585#M94076</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-04-03T07:46:40Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620586#M94077</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;thanks for your reply. I will ask the expert team for helping this issue. I will let you know when I get the reply.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Apr 2017 02:23:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620586#M94077</guid>
      <dc:creator>jimmychan</dc:creator>
      <dc:date>2017-04-05T02:23:16Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620587#M94078</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;could you tell me who is the customer?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Apr 2017 02:44:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620587#M94078</guid>
      <dc:creator>jimmychan</dc:creator>
      <dc:date>2017-04-05T02:44:30Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SX eMMC boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620588#M94079</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/jimmychan"&gt;jimmychan&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have sent a message to you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Apr 2017 03:18:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SX-eMMC-boot/m-p/620588#M94079</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-04-05T03:18:29Z</dc:date>
    </item>
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