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    <title>i.MX Processorsのトピックi.MX7 DDR Rd/Wr Delay Registers</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Rd-Wr-Delay-Registers/m-p/620141#M94001</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Can anyone confirm the name of the i.MX7 PHY registers used for DDR Read and Write delay values obtained from the DDR Stress Test tool..&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I suspect its DDR_PHY_OFFSET_RD_CON0 and DDR_PHY_OFFSET_WR_CON0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 01 Nov 2016 15:14:17 GMT</pubDate>
    <dc:creator>davidgeorge</dc:creator>
    <dc:date>2016-11-01T15:14:17Z</dc:date>
    <item>
      <title>i.MX7 DDR Rd/Wr Delay Registers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Rd-Wr-Delay-Registers/m-p/620141#M94001</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Can anyone confirm the name of the i.MX7 PHY registers used for DDR Read and Write delay values obtained from the DDR Stress Test tool..&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I suspect its DDR_PHY_OFFSET_RD_CON0 and DDR_PHY_OFFSET_WR_CON0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 01 Nov 2016 15:14:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Rd-Wr-Delay-Registers/m-p/620141#M94001</guid>
      <dc:creator>davidgeorge</dc:creator>
      <dc:date>2016-11-01T15:14:17Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX7 DDR Rd/Wr Delay Registers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Rd-Wr-Delay-Registers/m-p/620142#M94002</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Correct - DDR_PHY_OFFSET_RD_CON0 and DDR_PHY_OFFSET_WR_CON0. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Yuri&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note: If this post answers your question, please click the Correct &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Answer button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Nov 2016 04:51:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX7-DDR-Rd-Wr-Delay-Registers/m-p/620142#M94002</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-11-02T04:51:52Z</dc:date>
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