topic Re: About ddr frequency change in i.MX Processors

About ddr frequency change

MasakiHayakawa — Tue, 01 Nov 2016 01:53:31 GMT

Hi,

Android version is ICS, NXP patch name is imx-android-13.4.1.

Target platform is custom board of epdc system on i.MX6DualLite.

The configuration is two Micro 1GBx32 LPDDR2 in a dual-channel interleaved, 64-bit wide memory system.

We donwloaded patch files on the following site, files are 0001-Support-LPDDR2-on-6DL-platform_Uboot and 0001-Support-LPDDR2-on-6DL-platform_Kernel, and applied.

https://community.nxp.com/docs/DOC-94922

But after lpddr2 frequency change from 24MHz to 400MHz, kernel frequenctly freeze with dump messages.

We removed CON_REQ bit control of MMDCx_MDSCR register when lpddr2 frequency change entry and ext (file:arch/arm/mach-mx6/mx6_lpddr_freq.S), and it appears to be stable.

We refered to fsl-yocto-L4.1.15_1.2.0-ga.

Please tell me whether CON_REQ bit control of MMDCx_MDSCR register is need or not.

We think that this control is need... why did you remove this control on fsl-yocto-L4.1.15_1.2.0-ga ?

Best Regards.

Masaki Hayakawa

Re: About ddr frequency change

igorpadykov — Tue, 01 Nov 2016 05:13:10 GMT

Hi Masaki

recommended to use latest lpddr2 codes, also please check lpddr2 scm patches

SCM-i.MX 6Dual/6Quad Linux Patch not able to bitbake

note, for i.MX6DualLite arch/arm/mach-imx/lpddr2_freq_imx6q.S should be used

linux-2.6-imx.git - Freescale i.MX Linux Tree

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: About ddr frequency change

MasakiHayakawa — Thu, 03 Nov 2016 07:07:06 GMT

Hi igor,

Thank you for reply.

We have question about CON_REQ bit.

We refered i.MX6 Solo/DualLIte Applications Processor Reference Manual.

The CON_REQ bit description in MMDCx_MDSCR field descriptions is the following.

Configuration request/acknowledge mechanism should be used for the following procedures:

changing of timing parameters, during calibration process or driving commands via MDSCR[CMD].

We checked attachment file (arch/arm/mach-imx/lpddr2_freq_imx6q.S).

This file change timing parameters (MMDCx_CFG0,MMDCx_CFG1,MMDCx_CFG2,etc).

The CON_REQ bit control is need, isn't it ?

And please tell me LPDDR2 sequence about frequency change entry/exit.

Best Regards.