topic Re: Issue in setting SSIn parent clock to PLL4 in i.MX6 4.1.15 kernel in i.MX Processors

Issue in setting SSIn parent clock to PLL4 in i.MX6 4.1.15 kernel

shabeerbadarudh — Fri, 13 Jan 2017 17:16:10 GMT

Hi All,

In our custom board, we have porting linux kernel from 3.10.17 to 4.1.15.
we are facing some issues with microphone custom audio driver (chip :ICS-43432, issue : missing some samples),which is working perfectly in 3.10.17.

We have compared the audio clocks in 3.10.17 and 4.1.15, both are different. In 3.10.17 clock values IMX6_AUDIO_I2S_BCK, IMX6_AUDIO_I2S_FRCK are 3.078MHz and 48.108KHz and in 4.1.15 it is 2.88MHz and 54 KHz.

Then we have compared the clock source code in both kernel (arch/arm/mach-imx/clk-imx6q.c ) and noticed some difference. We want to derive ssi1_sel clock from PLL4. In 3.10.17 code for that configuration is present but not in 4.1.15 . So i have tried to set this in 4.1.15 kernel using the function 'imx_clk_set_parent(clk[IMX6QDL_CLK_SSI1_SEL],clk[IMX6QDL_CLK_PLL4_AUDIO])',
but it gives an error at boot time, 'failed to set parent of clk ssi1_sel to pll4_audio: -22'.

may i know the reason for these error or how do we set/configure the parent clocks in 4.1.15?

Thanks,

Shabeer

Re: Issue in setting SSIn parent clock to PLL4 in i.MX6 4.1.15 kernel

igorpadykov — Thu, 19 Jan 2017 00:39:45 GMT

Hi Shabeer

available clock selections listed in linux/include/dt-bindings/clock/imx6qdl-clock.h,

if clock is not available one can add it using description of common linux clock framework

https://www.kernel.org/doc/Documentation/clk.txt

http://elinux.org/images/b/b8/Elc2013_Clement.pdf

example of lcd clock selection

https://community.nxp.com/thread/434986

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: Issue in setting SSIn parent clock to PLL4 in i.MX6 4.1.15 kernel

shabeerbadarudh — Thu, 19 Jan 2017 10:07:29 GMT

Hi igorpadykov

Thanks for the response.

I have resolved my issue.

Re: Issue in setting SSIn parent clock to PLL4 in i.MX6 4.1.15 kernel

titusstalin — Tue, 26 Jun 2018 14:23:46 GMT

Hi Shabeer,

Can you please share me the dts changes for the ICS-43432 chip ?

I would like to interface this chip to i.MX6.

Thanks for the help.

Re: Issue in setting SSIn parent clock to PLL4 in i.MX6 4.1.15 kernel

shabeerbadarudh — Tue, 28 Aug 2018 10:25:47 GMT

Hi Titus,

Sorry for the late response, have you need any help from me?