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    <title>topic Re: iMX6 Solo Dual Lite Camera Preview in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Solo-Dual-Lite-Camera-Preview/m-p/613834#M92790</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Soumya&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;from sources: adv7180_write_reg (0x04,0x4E); //Output to BT656 mode&lt;/P&gt;&lt;P&gt;as sensor conifured in BT656 mode, so IPU should be configured to CCIR mode (BT.656) too&lt;/P&gt;&lt;P&gt;..&amp;nbsp; ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_SENS_PRTCL, clock_mode)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 08 Feb 2017 09:50:05 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2017-02-08T09:50:05Z</dc:date>
    <item>
      <title>iMX6 Solo Dual Lite Camera Preview</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Solo-Dual-Lite-Camera-Preview/m-p/613833#M92789</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;BR /&gt;Hi All,&lt;/P&gt;&lt;P&gt;I am trying to get a camera preview up using iMX6 Solo DualLite IPU. The Analog camera gives CVBS input to ADV7180 decoder. THe decoder gives 8-bit parallel CSI output&amp;nbsp;to the IPU. THe IPU is connected to a tianna display. I am using iMX6 Platform SDK as the base. Below are the configurations I have created to get the camera preview. What should be the configurations for FLOW registers in my case? I am getting noise on the display. I see that the DMA is hapenning and I get a DMA EOF interrupt and Interrupt Status registers 9 and 10 are clear with no errors. Many thanks for the replies.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;//Init ADV 7180 registers&lt;/P&gt;&lt;P&gt;adv7180_init();&lt;/P&gt;&lt;P&gt;adv7180_swrite_reg (0x0C,0x37);&amp;nbsp;//Put ADV7180 into Free Run mode&lt;/P&gt;&lt;P&gt;adv7180_write_reg (0x04,0x4E); //Output to BT656 mode&lt;/P&gt;&lt;P&gt;panel-&amp;gt;panel_init(&amp;amp;ipu_index);&amp;nbsp;//Init display panel&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;//IDMAC Configuration for CSI-&amp;gt;SFMC-&amp;gt;MEM&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;idmac_info.channel = CSI_TO_MEM_CH0;&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;idmac_info.addr0 = csi_mem0; //CH23_EBA0 - 0x40000000&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;idmac_info.addr1 = csi_mem1; // 0 - no double buffering&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;idmac_info.width = in_fmt-&amp;gt;active_width;&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;idmac_info.height = in_fmt-&amp;gt;active_height;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;csi_pixel_format = INTERLEAVED_RGB565;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_general_idmac_config(ipu_index, &amp;amp;idmac_info);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;//100 CSI1, ID=0 mapped to DMASMFC channel 0.&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_smfc_fifo_allocate(ipu_index, 0, 4, 4);&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_channel_buf_ready(ipu_index, CSI_TO_MEM_CH0, 0); //BUF_RDY&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;//CSI Configuration&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_IPU_CONF__CSI_SEL, 1);&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_IPU_CONF__CSI1_EN, 1);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_DATA_EN_POL, 0);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_EXT_VSYNC, 1);&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_SENS_PIX_CLK_POL, 0); // pos edge&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_DATA_POL, 0);&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_HSYNC_POL, hsync_pol);&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_VSYNC_POL, vsync_pol);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_DATA_DEST, 4); //destination is IDMAC via SFMC &lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_SENS_PRTCL, clock_mode); // Gated clock mode&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_DATA_WIDTH, 1); //8bits per color&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_PACK_TIGHT, 0); //only when data format is RGB/YUV, and &amp;nbsp;&amp;nbsp;&amp;nbsp;data_width &amp;gt; 8&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_SENS_DATA_FORMAT, data_fmt);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;/*set sensor frame size */&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_FRM_SIZE__CSI1_SENS_FRM_HEIGHT, raw_height - 1);&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_CSI1_SENS_FRM_SIZE__CSI1_SENS_FRM_WIDTH, raw_width - 1);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;//setup display&lt;BR /&gt;ipu_display_setup(ipu_index, CH23_EBA0, (uint32_t) NULL, INTERLEAVED_RGB565, panel);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;//Setup FLow&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL, 0x09); //DP_SYNC0 (ch23)&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_IPU_FS_PROC_FLOW3__SMFC0_DEST_SEL, 0x9); // smfc0 -&amp;gt; chan23&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_write_field(ipu_index, IPU_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL, 0x1); // MG source from capture 0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;//Enable Display and capture&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_enable_display(ipu_index);&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;ipu_idmac_channel_enable(ipu_index, CSI_TO_MEM_CH0, 1);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks and Best Regards,&lt;/P&gt;&lt;P&gt;Soumya&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Feb 2017 04:52:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Solo-Dual-Lite-Camera-Preview/m-p/613833#M92789</guid>
      <dc:creator>soumyaks</dc:creator>
      <dc:date>2017-02-08T04:52:38Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 Solo Dual Lite Camera Preview</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Solo-Dual-Lite-Camera-Preview/m-p/613834#M92790</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Soumya&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;from sources: adv7180_write_reg (0x04,0x4E); //Output to BT656 mode&lt;/P&gt;&lt;P&gt;as sensor conifured in BT656 mode, so IPU should be configured to CCIR mode (BT.656) too&lt;/P&gt;&lt;P&gt;..&amp;nbsp; ipu_write_field(ipu_index, IPU_CSI1_SENS_CONF__CSI1_SENS_PRTCL, clock_mode)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Feb 2017 09:50:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Solo-Dual-Lite-Camera-Preview/m-p/613834#M92790</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-02-08T09:50:05Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 Solo Dual Lite Camera Preview</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Solo-Dual-Lite-Camera-Preview/m-p/613835#M92791</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Instead of changing that,&amp;nbsp;I changed the decoder configuration to ouput 16-bit at LLC 4:2:2. (Gated mode clock)&lt;/P&gt;&lt;P&gt;However I get the same output (yellow). &amp;nbsp;Further, Even if I do not give any output from decoder (decoder intentionally not initialized), I am getting the same yellow output. If I memset the &lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;CH23_EBA0 to 0xff (white) and then do a DMA with above configuration, even then I get a yellow output. So I do get a new frame, but I am confused if it is doing a DMA from CSI-SMFC-MEM or not as the output is not differing. Kindly help..&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Many thanks in advance,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Soumya&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Feb 2017 10:40:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Solo-Dual-Lite-Camera-Preview/m-p/613835#M92791</guid>
      <dc:creator>soumyaks</dc:creator>
      <dc:date>2017-02-08T10:40:26Z</dc:date>
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