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    <title>i.MX ProcessorsのトピックRe: MII &amp; RGMII</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MII-RGMII/m-p/613029#M92579</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;As far as I can see RGMII doesn't use any of the pins of the MII, where does the multiplexing takes place?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Eli&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 31 Oct 2016 14:55:53 GMT</pubDate>
    <dc:creator>eliaz</dc:creator>
    <dc:date>2016-10-31T14:55:53Z</dc:date>
    <item>
      <title>MII &amp; RGMII</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MII-RGMII/m-p/613027#M92577</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;I asked beforehand about imx6q's ability to use RGMII &amp;amp; MII peripheries&amp;nbsp;&amp;nbsp;in the same time (Can these peripheries be active in the same time)?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;answer:&lt;/SPAN&gt; IMX6Q has ENET module, which supports MII, RMII, RGMII interfaces Pins affected are described in Table 23-1 (ENET External Signals) of the i.MX6 RM (Rev. 3, 07/2015). Only single interface may be used at a time because of multiplexing.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;what is the origin of multiplexing?&amp;nbsp;is it pin mux or other kind?&lt;/P&gt;&lt;P&gt;please elaborate.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Eli&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 30 Oct 2016 12:02:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MII-RGMII/m-p/613027#M92577</guid>
      <dc:creator>eliaz</dc:creator>
      <dc:date>2016-10-30T12:02:59Z</dc:date>
    </item>
    <item>
      <title>Re: MII &amp; RGMII</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MII-RGMII/m-p/613028#M92578</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, the IOMUX multiplexing is meant here.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Moreover, i.MX6Q has only single Ethernet MAC core, so, only one PHY and only one Ethernet interface can be used at a time.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 31 Oct 2016 11:21:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MII-RGMII/m-p/613028#M92578</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-10-31T11:21:05Z</dc:date>
    </item>
    <item>
      <title>Re: MII &amp; RGMII</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MII-RGMII/m-p/613029#M92579</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;As far as I can see RGMII doesn't use any of the pins of the MII, where does the multiplexing takes place?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Eli&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 31 Oct 2016 14:55:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MII-RGMII/m-p/613029#M92579</guid>
      <dc:creator>eliaz</dc:creator>
      <dc:date>2016-10-31T14:55:53Z</dc:date>
    </item>
    <item>
      <title>Re: MII &amp; RGMII</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MII-RGMII/m-p/613030#M92580</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;When the RGMII interface is selected, the MII signals become non-functional. So, as I told before, only one interface is functional at a time.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 01 Nov 2016 09:49:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MII-RGMII/m-p/613030#M92580</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-11-01T09:49:49Z</dc:date>
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