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    <title>i.MX ProcessorsのトピックInvalidatin Cortex-A9 SCU</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Invalidatin-Cortex-A9-SCU/m-p/612606#M92492</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi !&lt;/P&gt;&lt;P&gt;I'm trying to understand how to enable ACTLR.SMP and the SCU on our own secure OS, and the Cortex-A9 TRM states that:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;For the primary processor:&lt;BR /&gt;1. Invalidate:&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;• the SCU duplicate tags for all processors&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;• the data cache.&lt;BR /&gt;2. Enable the SCU.&lt;BR /&gt;3. Enable the data cache, set the SMP mode with ACTLR.SMP=1.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;While reading Linux code, I found that the SCU is enabled quite late in the boot process (mmu is already on, and L1/L2 caches are already configured), and the only bit set at this time are ENABLE and STANDBY_ENABLE. I can't find any invalidation of the SCU tags.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Is not invalidating the SCU before enabling an issue ?&lt;/LI&gt;&lt;LI&gt;Why does Linux enables the SCU so late in the boot process ?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Best,&lt;/P&gt;&lt;P&gt;V.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 12 Sep 2016 14:48:47 GMT</pubDate>
    <dc:creator>vsiles</dc:creator>
    <dc:date>2016-09-12T14:48:47Z</dc:date>
    <item>
      <title>Invalidatin Cortex-A9 SCU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Invalidatin-Cortex-A9-SCU/m-p/612606#M92492</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi !&lt;/P&gt;&lt;P&gt;I'm trying to understand how to enable ACTLR.SMP and the SCU on our own secure OS, and the Cortex-A9 TRM states that:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;For the primary processor:&lt;BR /&gt;1. Invalidate:&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;• the SCU duplicate tags for all processors&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;• the data cache.&lt;BR /&gt;2. Enable the SCU.&lt;BR /&gt;3. Enable the data cache, set the SMP mode with ACTLR.SMP=1.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;While reading Linux code, I found that the SCU is enabled quite late in the boot process (mmu is already on, and L1/L2 caches are already configured), and the only bit set at this time are ENABLE and STANDBY_ENABLE. I can't find any invalidation of the SCU tags.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Is not invalidating the SCU before enabling an issue ?&lt;/LI&gt;&lt;LI&gt;Why does Linux enables the SCU so late in the boot process ?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Best,&lt;/P&gt;&lt;P&gt;V.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Sep 2016 14:48:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Invalidatin-Cortex-A9-SCU/m-p/612606#M92492</guid>
      <dc:creator>vsiles</dc:creator>
      <dc:date>2016-09-12T14:48:47Z</dc:date>
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    <item>
      <title>Re: Invalidatin Cortex-A9 SCU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Invalidatin-Cortex-A9-SCU/m-p/612607#M92493</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; It is assumed, that the SCU after POR is invalidated.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Yuri&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note: If this post answers your question, please click the Correct &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Answer button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Oct 2016 07:42:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Invalidatin-Cortex-A9-SCU/m-p/612607#M92493</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-10-10T07:42:14Z</dc:date>
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