i.MX ProcessorsのトピックRe: Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT

Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT

eishishibusawa — Thu, 12 Jan 2017 05:25:01 GMT

Dear Sir

I want to confirm about the Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT.

I refer to the i.MX6DulaLite reference manual (IMX6SDLRM Rev.2) .

It is described as the follows.

At P796

Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT = 540(MHz)

At P996

ACLK: EIM clock (main clock, AXI clock) with a Max frequency of 133Mhz.

(ACLK = ACLK_EIM_SLOW_CLK_ROOT)

I think that it means the Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT = 133(MHz).

I refer to the i.MX6DualLite (Auto) Data sheet (IMX6SDLAEC Rev.7).

It is described at P52 in the RM as following.

The maximum frequency for CLK_EIM_SLOW_CLK_ROOT is 132 MHz.

Q1.

What is the correct Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT?

Customer said that the default setting of the ACLK_EIM_SLOW_CLK_ROOT in Linux BSP from NXP is 135MHz.

Q2.

Can we understand that we should modify the setting of the ACLK_EIM_SLOW_CLK_ROOT for below 132MHz?

Best Regards,

Eishi SHIBUSAWA

Re: Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT

Yuri — Thu, 12 Jan 2017 08:42:13 GMT

Hello

Looking at Figure 18-2 (Clock Tree - Part 1) and section 18.6.8 [CCM Serial Clock

Multiplexer Register 1 (CCM_CSCMR1)] of the recent RM we can find, that the following

sources may be selected :

00 derive clock from AXI

01 derive clock from pll3_sw_clk

10 derive clock from PLL2 PFD2

11 derive clock from PLL2 PFD0

By default, aclk_eim_slow is sourced from AXI clock root ; it is needed to take
into account CBCDR[AXI_PODF] divider, and the divide-by-2, so it is 135 MHz.

Without dividers, theoretically 540 MHz may be set, but the Datasheet provides
real data, which was successfully tested under all possible operational conditions

(temperature, voltages ).

Have a great day,
Yuri

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Re: Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT

eishishibusawa — Thu, 12 Jan 2017 09:16:12 GMT

Dear Yuri

Customer want to know the Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT, which NXP guarantees operation.

"the Datasheet provides real data, which was successfully tested under all possible operational conditions (temperature, voltages )."

Refer to your answer.

Q1.

Can I understand that the maximum frequency of ACLK_EIM_SLOW_CLK_ROOT is 132MHz?

Best Regards,

Eishi SHIBUSAWA

Re: Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT

yuhe-r64908 — Thu, 26 Jan 2017 04:29:33 GMT

Hi Yuri,

I think there are the following mistakes in IMX6SDLRM(Rev. 2, 04/2015).

1. Table 18-4 at P. 796
The Default Frequency(MHZ) of ACLK_EIM_SLOW_CLK_ROOT should be 135 instead of 198

2. "22.3 Clocks" at P.996

"ACLK: EIM clock (main clock, AXI clock) with a Max frequency of 133Mhz. Can be gated externally when there is no active AXI access."
should be

"ACLK: EIM clock (main clock, AXI clock) with a Max frequency of 132Mhz. Can be gated externally when there is no active AXI access."

Could you give the feedback to BL for RM correction ?

Thanks,
Yu

Re: Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT

Yuri — Thu, 26 Jan 2017 07:14:21 GMT

Hello,

From the DataSheet :

" The maximum allowed axi_clk frequency depends on the fixed/non-fixed
latency configuration, whereas the maximum allowed EIM_BCLK frequency is:
—Fixed latency for both read and write is 104 MHz.
—Variable latency for read only is 104 MHz.
—Variable latency for write only is 52 MHz.
In variable latency configuration for write, if BCD = 0 & WBCDD = 1 or BCD = 1, axi_clk must be 104 MHz.Write BCD = 1 and 104 MHz ACLK_EXSC, will result in a EIM_BCLK of 52 MHz. When the clock branch to EIM is decreased to 104 MHz, other buses are impacted which are clocked from this source."

Regards,

Yuri.

Re: Maximum Frequency of ACLK_EIM_SLOW_CLK_ROOT

Yuri — Thu, 26 Jan 2017 07:47:29 GMT

Hello,

I am not sure if the RM can be changed in the nearest future ; for practical using maximum

external EIM frequency is important - this value is provided in the Datasheets, as shown in my
reply above.

Regards,

Yuri.