i.MX Processors中的主题 Re: i.MX6UL, MMDC_MDMISC register https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-MMDC-MDMISC-register/m-p/609835#M91976 <HTML><HEAD></HEAD><BODY><P>Thank you very much for your answer!</P><P>Tomas</P></BODY></HTML> Wed, 08 Feb 2017 13:02:58 GMT tomasjun 2017-02-08T13:02:58Z i.MX6UL, MMDC_MDMISC register https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-MMDC-MDMISC-register/m-p/609833#M91974 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P>please&nbsp;I need describe exactly bit 31 of MMDC_MDMISC register,</P><P>CS0_RDY: 0 Device in wake-up period / 1 Device is ready for initialization</P><P>What is "normal state" -&nbsp; Wake-up or Device ready ... ?</P><P>Thank you for cooperation.</P><P>Tomas</P></BODY></HTML> Thu, 12 Jan 2017 14:28:09 GMT https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-MMDC-MDMISC-register/m-p/609833#M91974 tomasjun 2017-01-12T14:28:09Z Re: i.MX6UL, MMDC_MDMISC register https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-MMDC-MDMISC-register/m-p/609834#M91975 <HTML><HEAD></HEAD><BODY><P>Hello Tomas Jun,</P><P></P><P>The CS0_RDY bit is cleared at reset or during deep power-down entry of the memory. This bit is set after the wake-up period, when the memory is ready for transfers which you may call normal state.</P><P></P><P>I hope this information helps!</P><P>Regards,</P></BODY></HTML> Wed, 18 Jan 2017 18:32:28 GMT https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-MMDC-MDMISC-register/m-p/609834#M91975 gusarambula 2017-01-18T18:32:28Z Re: i.MX6UL, MMDC_MDMISC register https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-MMDC-MDMISC-register/m-p/609835#M91976 <HTML><HEAD></HEAD><BODY><P>Thank you very much for your answer!</P><P>Tomas</P></BODY></HTML> Wed, 08 Feb 2017 13:02:58 GMT https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-MMDC-MDMISC-register/m-p/609835#M91976 tomasjun 2017-02-08T13:02:58Z