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    <title>topic Re: DDR3 Memory bus IMX6DL in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DDR3-Memory-bus-IMX6DL/m-p/608375#M91751</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;size is defined by MMDCx_MDCTL[DSIZ]&amp;nbsp;DDR data bus size. Also one can check presentation on&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-331528"&gt;DES-N1936 i.MX 6UltraLite DDR Tools Overview and Hardware Design Considerations.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 28 Oct 2016 13:30:21 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-10-28T13:30:21Z</dc:date>
    <item>
      <title>DDR3 Memory bus IMX6DL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3-Memory-bus-IMX6DL/m-p/608372#M91748</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would like to use an IMX6 Dual Lite with less than 4 DDR3 chips, so in 16 or 32 bit DDR3 mode&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Somebody can tell if this is possible ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Oct 2016 14:28:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3-Memory-bus-IMX6DL/m-p/608372#M91748</guid>
      <dc:creator>sebastien_puel</dc:creator>
      <dc:date>2016-10-27T14:28:13Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3 Memory bus IMX6DL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3-Memory-bus-IMX6DL/m-p/608373#M91749</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sébastien&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes this is possible&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Oct 2016 23:21:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3-Memory-bus-IMX6DL/m-p/608373#M91749</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-10-27T23:21:59Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3 Memory bus IMX6DL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3-Memory-bus-IMX6DL/m-p/608374#M91750</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for this answer.&lt;/P&gt;&lt;P&gt;Have you any datasheet or application note for bus use in 16 or 32 bit ?&amp;nbsp;&lt;/P&gt;&lt;P&gt;I find documentation only for 1x64 bit (DDR3) or 2x32 bit (LP-DDR2).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Sébastien&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Oct 2016 09:04:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3-Memory-bus-IMX6DL/m-p/608374#M91750</guid>
      <dc:creator>sebastien_puel</dc:creator>
      <dc:date>2016-10-28T09:04:31Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3 Memory bus IMX6DL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3-Memory-bus-IMX6DL/m-p/608375#M91751</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;size is defined by MMDCx_MDCTL[DSIZ]&amp;nbsp;DDR data bus size. Also one can check presentation on&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-331528"&gt;DES-N1936 i.MX 6UltraLite DDR Tools Overview and Hardware Design Considerations.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Oct 2016 13:30:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3-Memory-bus-IMX6DL/m-p/608375#M91751</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-10-28T13:30:21Z</dc:date>
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