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    <title>topic Re: IMX6Q uart FIFO overrun in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-uart-FIFO-overrun/m-p/606332#M91388</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/weidong.sun"&gt;weidong.sun&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;I update the driver code drivers/tty/serial/imx.c to 3.18.30 kernel, and modified it to enable SDMA on UART whether flow control enabled or disabled. I set the CPU scaling governor to performance incidentally. However, it seems just better than before. The RX FIFO still overrun random.&amp;nbsp;Is it necessary&amp;nbsp;to add some hardware flow control like CTS/RTS to ensure enough baud rate on UART?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 18 Apr 2017 02:12:05 GMT</pubDate>
    <dc:creator>mostion</dc:creator>
    <dc:date>2017-04-18T02:12:05Z</dc:date>
    <item>
      <title>IMX6Q uart FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-uart-FIFO-overrun/m-p/606329#M91385</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;We use the IMX6 processor for some time now. But recently, we need use one uart port at 460800 baud, and then, we found some system error message said Rx FIFO overrun. We check the drivers code repeatedly, and make some test for it, but we have no idea for this issue. Anyway, if the baud is larger than 115200, like 230400, the Rx FIFO always overrun. We attempt to disable all function unused, just remain some necessities about uart, but it not worked.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;By the way, we have a platform used the IMX535 processor run&amp;nbsp;same&amp;nbsp;baud on uart, but it seemed everything is OK.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;On the other side, we update some later driver code, it also can not fix this. Our Linux kernel is 3.10.17.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Please, if some guys have any ideas about this, give some suggestions.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Apr 2017 07:41:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-uart-FIFO-overrun/m-p/606329#M91385</guid>
      <dc:creator>mostion</dc:creator>
      <dc:date>2017-04-13T07:41:52Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6Q uart FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-uart-FIFO-overrun/m-p/606330#M91386</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A _jive_internal="true" class="" data-content-finding="Community" data-userid="297971" data-username="mostion" href="https://community.nxp.com/people/mostion"&gt;Mostion&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The issue you encountered should be the reason why processor can't read RX FIFO in time, so you had better use SDMA for UART communications. This is can be set in device tree.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;TIC&amp;nbsp; weidong&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Apr 2017 08:57:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-uart-FIFO-overrun/m-p/606330#M91386</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2017-04-13T08:57:10Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6Q uart FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-uart-FIFO-overrun/m-p/606331#M91387</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Wigros,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;I hope we can enable SDMA for UART, but the UART design just have&amp;nbsp;RX/TX line connected to TTL which means we could not enable any&amp;nbsp;flow control functions. I have checked the driver code, if we want to enable the SDMA for UART, the flow control need to enabled. Is it possible that I modify&amp;nbsp;the code to enable SDMA at this platform? If as you said,&amp;nbsp;do you&amp;nbsp;means that&amp;nbsp;this processor can't support&amp;nbsp;such large baud rate for&amp;nbsp;UART communication without flow control?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;And why our other platform which used IMX535 seems everything is OK? That platform design is same as this one, just the processor is different. If IMX6Q can't support this baud rate, the IMX535 ought to be same more.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Looking forward to your reply.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best Regards.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Apr 2017 09:34:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-uart-FIFO-overrun/m-p/606331#M91387</guid>
      <dc:creator>mostion</dc:creator>
      <dc:date>2017-04-13T09:34:45Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6Q uart FIFO overrun</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-uart-FIFO-overrun/m-p/606332#M91388</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/weidong.sun"&gt;weidong.sun&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;I update the driver code drivers/tty/serial/imx.c to 3.18.30 kernel, and modified it to enable SDMA on UART whether flow control enabled or disabled. I set the CPU scaling governor to performance incidentally. However, it seems just better than before. The RX FIFO still overrun random.&amp;nbsp;Is it necessary&amp;nbsp;to add some hardware flow control like CTS/RTS to ensure enough baud rate on UART?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 18 Apr 2017 02:12:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-uart-FIFO-overrun/m-p/606332#M91388</guid>
      <dc:creator>mostion</dc:creator>
      <dc:date>2017-04-18T02:12:05Z</dc:date>
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