topic Re: imx7 openocd tapid and debug base help in i.MX Processors

imx7 openocd tapid and debug base help

fatalfeel — Fri, 09 Sep 2016 03:16:06 GMT

here is imx6 tap id in openocd

# System JTAG Controller
if { [info exists SJC_TAPID] } {
set _SJC_TAPID $SJC_TAPID
} else {
set _SJC_TAPID 0x0191c01d
}

# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
}

target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x82150000 (CoreSight base)

Whats is imx7 _DAP_TAPID _SJC_TAPID and debug base??? can not find need help

Re: imx7 openocd tapid and debug base help

anthonybrunebar — Fri, 09 Sep 2016 13:17:38 GMT

Hi Jesse Stone,

_DAP_TAPID for imx7 is 0x5BA00477. i found it in chapter "4.11.1.4.1 Debug Access Port (DAP) TAP" of the imx7D reference manual.

Re: imx7 openocd tapid and debug base help

fatalfeel — Fri, 09 Sep 2016 20:21:09 GMT

Roger that

still need SJC_TAPID address and debug base address(coresight)

Re: imx7 openocd tapid and debug base help

fatalfeel — Fri, 09 Sep 2016 21:11:54 GMT

some info for general cortex a7

openocd-targets/ls1021a.cfg at master · 4mig4/openocd-targets · GitHub

openocd code modify for cortex-A7

Olimex ARM-USB-OCD-H / openocd-0.9.0 / libftd2xx1.1.12 / Raspberry Pi 2 / Ubuntu 15.04 · GitHub

Re: imx7 openocd tapid and debug base help

igorpadykov — Fri, 09 Sep 2016 23:29:58 GMT

Hi jesse

in general one can check ds5 configs :

https://community.arm.com/groups/tools/blog/2016/02/24/getting-started-with-ds-5-and-imx7
http://developer.toradex.com/knowledge-base/using-arm-ds-5-ide-with-cortex-m4-of-a-colibri-imx7

Best regards
igor
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Re: imx7 openocd tapid and debug base help

fatalfeel — Sat, 10 Sep 2016 02:09:17 GMT

thanks a lot sir~~~~

<scanchain>
            <dap name="ARMCS-DP" type="ARMCS-DP">
                <device_info_items>
                    <device_info_item name="JTAG_IDCODE">0x5BA00477</device_info_item>
                </device_info_items>
                <device name="CSMEMAP_0" type="CSMEMAP">
                    <config_items>
                        <config_item name="CORESIGHT_AP_INDEX">0</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="AP_TYPE">AHB-AP</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSMEMAP_1" type="CSMEMAP">
                    <config_items>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="AP_TYPE">APB-AP</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSCTI_3" type="CSCTI">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x80089000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                </device>
                <device name="CSCTI_4" type="CSCTI">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x00000000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                </device>
                <device name="CSTPIU_0" type="CSTPIU">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x80087000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                </device>
                <device name="CSTMC_0" type="CSTMC">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x80084000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="CONFIG_TYPE">ETF</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSTMC_1" type="CSTMC">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x80086000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="CONFIG_TYPE">ETR</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSTFunnel_0" type="CSTFunnel">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x80041000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                </device>
                <device name="CSTFunnel_1" type="CSTFunnel">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x80083000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                </device>
                <device name="Cortex-A7" type="Cortex-A7">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x80070000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="PERIPHERAL_ID">0x00000C07</device_info_item>
                        <device_info_item name="JEP_ID">0x0000043B</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSCTI_0" type="CSCTI">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x80078000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                </device>
                <device name="CSCTI_1" type="CSCTI">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x80079000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                </device>
                <device name="CSETM_0" type="CSETM">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x8007C000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="VERSION"/>
                        <device_info_item name="SUPPORTS_CONTEXT_IDS"/>
                        <device_info_item name="SUPPORTS_CYCLE_ACCURATE"/>
                        <device_info_item name="SUPPORTS_DATA_ONLY_MODE"/>
                        <device_info_item name="SUPPORTS_TIMESTAMPS"/>
                    </device_info_items>
                </device>
                <device name="CSPMU" type="CSPMU">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0x80071000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">1</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="PERIPHERAL_ID">0x000009A7</device_info_item>
                        <device_info_item name="JEP_ID">0x0000043B</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSMEMAP_2" type="CSMEMAP">
                    <config_items>
                        <config_item name="CORESIGHT_AP_INDEX">2</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="AP_TYPE">JTAG-AP</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSMEMAP_3" type="CSMEMAP">
                    <config_items>
                        <config_item name="CORESIGHT_AP_INDEX">3</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="AP_TYPE">JTAG-AP</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSMEMAP_4" type="CSMEMAP">
                    <config_items>
                        <config_item name="CORESIGHT_AP_INDEX">4</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="AP_TYPE">AHB-AP-M</device_info_item>
                    </device_info_items>
                </device>
                <device name="Cortex-M4" type="Cortex-M4">
                    <config_items>
                        <config_item name="CORESIGHT_AP_INDEX">4</config_item>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0xE000ED00</config_item>
                        <config_item name="JTAG_TIMEOUTS_ENABLED">False</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="PERIPHERAL_ID">0x00000474</device_info_item>
                        <device_info_item name="JEP_ID">0x0000043B</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSETM_1" type="CSETM">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0xE0041000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">4</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="VERSION">3.5</device_info_item>
                        <device_info_item name="SUPPORTS_CONTEXT_IDS">False</device_info_item>
                        <device_info_item name="SUPPORTS_CYCLE_ACCURATE">False</device_info_item>
                        <device_info_item name="SUPPORTS_DATA_ONLY_MODE">False</device_info_item>
                        <device_info_item name="SUPPORTS_TIMESTAMPS">True</device_info_item>
                        <device_info_item name="PERIPHERAL_ID">0x00000925</device_info_item>
                        <device_info_item name="JEP_ID">0x0000043B</device_info_item>
                        <device_info_item name="SUPPORTS_DATA_ADDR_TRACE">False</device_info_item>
                        <device_info_item name="SUPPORTS_DATA_VAL_TRACE">False</device_info_item>
                        <device_info_item name="SUPPORTS_TRACE_RANGE">False</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSTFunnel_2" type="CSTFunnel">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0xE0043000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">4</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="PERIPHERAL_ID">0x00000908</device_info_item>
                        <device_info_item name="JEP_ID">0x0000043B</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSCTI_2" type="CSCTI">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0xE0044000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">4</config_item>
                    </config_items>
                    <device_info_items>
                        <device_info_item name="PERIPHERAL_ID">0x00000906</device_info_item>
                        <device_info_item name="JEP_ID">0x0000043B</device_info_item>
                    </device_info_items>
                </device>
                <device name="CSITM" type="CSITM">
                    <config_items>
                        <config_item name="CORESIGHT_BASE_ADDRESS">0xE0000000</config_item>
                        <config_item name="CORESIGHT_AP_INDEX">4</config_item>
                    </config_items>
                </device>
            </dap>
        </scanchain>

Re: imx7 openocd tapid and debug base help

ed_yang — Sat, 10 Sep 2016 02:44:51 GMT

#Sucess

# Freescale i.MX7 series single/dual/quad core processor

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imx7
}

# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x5ba00477
}

jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID

# SDMA / no IDCODE
#jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f

# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
# core 0 - 0x82150000
# core 1 - 0x82152000
# core 2 - 0x82154000
# core 3 - 0x82156000
set _TARGETNAME $_CHIPNAME.cpu.0
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80070000

# some TCK cycles are required to activate the DEBUG power domain
#jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"

proc imx7_dbginit {target} {
# General Cortex A8/A9 debug initialisation
cortex_a dbginit
}

# Slow speed to be sure it will work
adapter_khz 1000
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }

$_TARGETNAME configure -event reset-assert-post "imx7_dbginit $_TARGETNAME"
$_TARGETNAME configure -event gdb-attach { halt }

Re: imx7 openocd tapid and debug base help

ed_yang — Sat, 10 Sep 2016 02:46:24 GMT

# shipped busblaster cfg
source /opt/openocd/share/openocd/scripts/interface/ftdi/dp_busblaster.cfg

# imx7 config
source /opt/openocd/share/openocd/scripts/target/imx7.cfg

jtag_ntrst_delay 1000

gdb_port 3333
telnet_port 4444

$_TARGETNAME configure -event reset-assert "imx7d_init"
$_TARGETNAME configure -event reset-end "clear_regs"

proc imx6d_ddr3_1GB_init {} {
puts "proc imx6d_ddr3_1GB_init ==> begin"

   # /bootable/bootloader/uboot-imx/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
   set MX6_IOM_DRAM_DQM0       0x020e05ac
   set MX6_IOM_DRAM_DQM1       0x020e05b4
   set MX6_IOM_DRAM_DQM2       0x020e0528
   set MX6_IOM_DRAM_DQM3       0x020e0520
   set MX6_IOM_DRAM_DQM4       0x020e0514
   set MX6_IOM_DRAM_DQM5       0x020e0510
   set MX6_IOM_DRAM_DQM6       0x020e05bc
   set MX6_IOM_DRAM_DQM7       0x020e05c4

   set MX6_IOM_DRAM_CAS        0x020e056c
   set MX6_IOM_DRAM_RAS        0x020e0578
   set MX6_IOM_DRAM_RESET      0x020e057c
   set MX6_IOM_DRAM_SDCLK_0    0x020e0588
   set MX6_IOM_DRAM_SDCLK_1    0x020e0594
   set MX6_IOM_DRAM_SDBA2      0x020e058c
   set MX6_IOM_DRAM_SDCKE0     0x020e0590
   set MX6_IOM_DRAM_SDCKE1     0x020e0598
   set MX6_IOM_DRAM_SDODT0     0x020e059c
   set MX6_IOM_DRAM_SDODT1     0x020e05a0

   set MX6_IOM_DRAM_SDQS0      0x020e05a8
   set MX6_IOM_DRAM_SDQS1      0x020e05b0
   set MX6_IOM_DRAM_SDQS2      0x020e0524
   set MX6_IOM_DRAM_SDQS3      0x020e051c
   set MX6_IOM_DRAM_SDQS4      0x020e0518
   set MX6_IOM_DRAM_SDQS5      0x020e050c
   set MX6_IOM_DRAM_SDQS6      0x020e05b8
   set MX6_IOM_DRAM_SDQS7      0x020e05c0

   set MX6_IOM_GRP_B0DS        0x020e0784
   set MX6_IOM_GRP_B1DS        0x020e0788
   set MX6_IOM_GRP_B2DS        0x020e0794
   set MX6_IOM_GRP_B3DS        0x020e079c
   set MX6_IOM_GRP_B4DS        0x020e07a0
   set MX6_IOM_GRP_B5DS        0x020e07a4
   set MX6_IOM_GRP_B6DS        0x020e07a8
   set MX6_IOM_GRP_B7DS        0x020e0748
   set MX6_IOM_GRP_ADDDS       0x020e074c
   set MX6_IOM_DDRMODE_CTL     0x020e0750
   set MX6_IOM_GRP_DDRPKE      0x020e0758
   set MX6_IOM_GRP_DDRMODE     0x020e0774
   set MX6_IOM_GRP_CTLDS       0x020e078c
   set MX6_IOM_GRP_DDR_TYPE    0x020e0798

   # /bootable/bootloader/uboot-imx/arch/arm/include/asm/arch-mx6/mx6-ddr.h
   set MX6_MMDC_P0_MDCTL       0x021b0000
   set MX6_MMDC_P0_MDPDC       0x021b0004
   set MX6_MMDC_P0_MDOTC       0x021b0008
   set MX6_MMDC_P0_MDCFG0      0x021b000c
   set MX6_MMDC_P0_MDCFG1      0x021b0010
   set MX6_MMDC_P0_MDCFG2      0x021b0014
   set MX6_MMDC_P0_MDMISC      0x021b0018
   set MX6_MMDC_P0_MDSCR       0x021b001c
   set MX6_MMDC_P0_MDREF       0x021b0020
   set MX6_MMDC_P0_MDRWD       0x021b002c
   set MX6_MMDC_P0_MDOR        0x021b0030
   set MX6_MMDC_P0_MDASP       0x021b0040
   set MX6_MMDC_P0_MAPSR       0x021b0404
   set MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
   set MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
   set MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
   set MX6_MMDC_P0_MPODTCTRL   0x021b0818
   set MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
   set MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
   set MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
   set MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
   set MX6_MMDC_P0_MPDGCTRL0   0x021b083c
   set MX6_MMDC_P0_MPDGCTRL1   0x021b0840
   set MX6_MMDC_P0_MPRDDLCTL   0x021b0848
   set MX6_MMDC_P0_MPWRDLCTL   0x021b0850
   set MX6_MMDC_P0_MPMUR0      0x021b08b8

   set MX6_MMDC_P1_MDCTL       0x021b4000
   set MX6_MMDC_P1_MDPDC       0x021b4004
   set MX6_MMDC_P1_MDOTC       0x021b4008
   set MX6_MMDC_P1_MDCFG0      0x021b400c
   set MX6_MMDC_P1_MDCFG1      0x021b4010
   set MX6_MMDC_P1_MDCFG2      0x021b4014
   set MX6_MMDC_P1_MDMISC      0x021b4018
   set MX6_MMDC_P1_MDSCR       0x021b401c
   set MX6_MMDC_P1_MDREF       0x021b4020
   set MX6_MMDC_P1_MDRWD       0x021b402c
   set MX6_MMDC_P1_MDOR        0x021b4030
   set MX6_MMDC_P1_MDASP       0x021b4040
   set MX6_MMDC_P1_MAPSR       0x021b4404
   set MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
   set MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
   set MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
   set MX6_MMDC_P1_MPODTCTRL   0x021b4818
   set MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
   set MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
   set MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
   set MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
   set MX6_MMDC_P1_MPDGCTRL0   0x021b483c
   set MX6_MMDC_P1_MPDGCTRL1   0x021b4840
   set MX6_MMDC_P1_MPRDDLCTL   0x021b4848
   set MX6_MMDC_P1_MPWRDLCTL   0x021b4850
   set MX6_MMDC_P1_MPMUR0      0x021b48b8

################################################
   # /bootable/bootloader/uboot-imx/board/freescale/imx/ddr/mx6q_4x_mt41j256.cfg
   # IOMUX
   # DDR IO type
   mww phys $MX6_IOM_GRP_DDR_TYPE 0x000C0000
   mww phys $MX6_IOM_GRP_DDRPKE   0x00000000

   # Clock
   mww phys $MX6_IOM_DRAM_SDCLK_0 0x00000028
   mww phys $MX6_IOM_DRAM_SDCLK_1 0x00000028

   # Address
   mww phys $MX6_IOM_DRAM_CAS     0x00000028
   mww phys $MX6_IOM_DRAM_RAS     0x00000028
   mww phys $MX6_IOM_GRP_ADDDS    0x00000028

   # Control
   mww phys $MX6_IOM_DRAM_RESET   0x00000028
   mww phys $MX6_IOM_DRAM_SDBA2   0x00000000
   mww phys $MX6_IOM_DRAM_SDODT0 0x00000028
   mww phys $MX6_IOM_DRAM_SDODT1 0x00000028
   mww phys $MX6_IOM_GRP_CTLDS    0x00000028

   # Data Strobes
   mww phys $MX6_IOM_DDRMODE_CTL 0x00020000
   mww phys $MX6_IOM_DRAM_SDQS0 0x00000028
   mww phys $MX6_IOM_DRAM_SDQS1 0x00000028
   mww phys $MX6_IOM_DRAM_SDQS2 0x00000028
   mww phys $MX6_IOM_DRAM_SDQS3 0x00000028
   mww phys $MX6_IOM_DRAM_SDQS4 0x00000028
   mww phys $MX6_IOM_DRAM_SDQS5 0x00000028
   mww phys $MX6_IOM_DRAM_SDQS6 0x00000028
   mww phys $MX6_IOM_DRAM_SDQS7 0x00000028

   # Data
   mww phys $MX6_IOM_GRP_DDRMODE 0x00020000
   mww phys $MX6_IOM_GRP_B0DS    0x00000028
   mww phys $MX6_IOM_GRP_B1DS    0x00000028
   mww phys $MX6_IOM_GRP_B2DS    0x00000028
   mww phys $MX6_IOM_GRP_B3DS    0x00000028
   mww phys $MX6_IOM_GRP_B4DS    0x00000028
   mww phys $MX6_IOM_GRP_B5DS    0x00000028
   mww phys $MX6_IOM_GRP_B6DS    0x00000028
   mww phys $MX6_IOM_GRP_B7DS    0x00000028
   mww phys $MX6_IOM_DRAM_DQM0   0x00000028
   mww phys $MX6_IOM_DRAM_DQM1   0x00000028
   mww phys $MX6_IOM_DRAM_DQM2   0x00000028
   mww phys $MX6_IOM_DRAM_DQM3   0x00000028
   mww phys $MX6_IOM_DRAM_DQM4   0x00000028
   mww phys $MX6_IOM_DRAM_DQM5   0x00000028
   mww phys $MX6_IOM_DRAM_DQM6   0x00000028
   mww phys $MX6_IOM_DRAM_DQM7   0x00000028

   ### Special Data write we do not have
   ## mww phys $MX6_MMDC_P0_MDSCR 0x00008000

   # Calibration setup
   mww phys $MX6_MMDC_P0_MPZQHWCTRL 0xa1390003

   # Leveling calibration (fine tune)
   mww phys $MX6_MMDC_P0_MPWLDECTRL0 0x00150011
   mww phys $MX6_MMDC_P0_MPWLDECTRL1 0x001F0017
   mww phys $MX6_MMDC_P1_MPWLDECTRL0 0x0001501F
   mww phys $MX6_MMDC_P1_MPWLDECTRL1 0x00060017

   # Read DQS Gating calibration (fine tune)
   mww phys $MX6_MMDC_P0_MPDGCTRL0 0x03280338
   mww phys $MX6_MMDC_P0_MPDGCTRL1 0x0320031C
   mww phys $MX6_MMDC_P1_MPDGCTRL0 0x0328033C
   mww phys $MX6_MMDC_P1_MPDGCTRL1 0x03240268

   # Read calibration (fine tune)
   mww phys $MX6_MMDC_P0_MPRDDLCTL 0x362E3038
   mww phys $MX6_MMDC_P1_MPRDDLCTL 0x38343040

   # Write calibration (fine tune)
   mww phys $MX6_MMDC_P0_MPWRDLCTL 0x3838423A
   mww phys $MX6_MMDC_P1_MPWRDLCTL 0x4636443C

   # Read data bit delay
   mww phys $MX6_MMDC_P0_MPRDDQBY0DL 0x33333333
   mww phys $MX6_MMDC_P0_MPRDDQBY1DL 0x33333333
   mww phys $MX6_MMDC_P0_MPRDDQBY2DL 0x33333333
   mww phys $MX6_MMDC_P0_MPRDDQBY3DL 0x33333333
   mww phys $MX6_MMDC_P1_MPRDDQBY0DL 0x33333333
   mww phys $MX6_MMDC_P1_MPRDDQBY1DL 0x33333333
   mww phys $MX6_MMDC_P1_MPRDDQBY2DL 0x33333333
   mww phys $MX6_MMDC_P1_MPRDDQBY3DL 0x33333333

   # Complete calibration by forced measurement
   mww phys $MX6_MMDC_P0_MPMUR0 0x00000800
   mww phys $MX6_MMDC_P1_MPMUR0 0x00000800

   # MMDC init
   mww phys $MX6_MMDC_P0_MDPDC 0x00020036
   mww phys $MX6_MMDC_P0_MDOTC 0x09444040
   mww phys $MX6_MMDC_P0_MDCFG0 0x898E7955
   mww phys $MX6_MMDC_P0_MDCFG1 0xFF328F64
   mww phys $MX6_MMDC_P0_MDCFG2 0x01FF00DB
   mww phys $MX6_MMDC_P0_MDMISC 0x00011740
   mww phys $MX6_MMDC_P0_MDSCR 0x00008000
   mww phys $MX6_MMDC_P0_MDRWD 0x000026d2
   mww phys $MX6_MMDC_P0_MDOR   0x008E1023
   mww phys $MX6_MMDC_P0_MDASP 0x00000047
   mww phys $MX6_MMDC_P0_MDCTL 0x841A0000

   # Mode register writes
   mww phys $MX6_MMDC_P0_MDSCR 0x02088032
   mww phys $MX6_MMDC_P0_MDSCR 0x00008033
   mww phys $MX6_MMDC_P0_MDSCR 0x00048031
   mww phys $MX6_MMDC_P0_MDSCR 0x19408030
   mww phys $MX6_MMDC_P0_MDSCR 0x04008040
   mww phys $MX6_MMDC_P0_MDREF 0x00007800
   mww phys $MX6_MMDC_P0_MPODTCTRL 0x00022227
   mww phys $MX6_MMDC_P1_MPODTCTRL 0x00022227
   mww phys $MX6_MMDC_P0_MDPDC     0x00025576
   mww phys $MX6_MMDC_P0_MAPSR     0x00011006
   mww phys $MX6_MMDC_P0_MDSCR     0x00000000
}

proc imx6_clock_init {} {
puts "proc imx6_clock_init ==> begin"

   # asm/arch-mx6/crm_regs.h
   set CCM_CCGR0 0x020C4068
   set CCM_CCGR1 0x020C406c
   set CCM_CCGR2 0x020C4070
   set CCM_CCGR3 0x020C4074
   set CCM_CCGR4 0x020C4078
   set CCM_CCGR5 0x020C407c
   set CCM_CCGR6 0x020C4080

   # Enable all clocks
   #mww phys $CCM_CCGR0 0xFFFFFFFF
   #mww phys $CCM_CCGR1 0xFFFFFFFF
   #mww phys $CCM_CCGR2 0xFFFFFFFF
   #mww phys $CCM_CCGR3 0xFFFFFFFF
   #mww phys $CCM_CCGR4 0xFFFFFFFF
   #mww phys $CCM_CCGR5 0xFFFFFFFF
   #mww phys $CCM_CCGR6 0xFFFFFFFF

   # default clocks
   mww phys $CCM_CCGR0 0x00C03F3F
   mww phys $CCM_CCGR1 0x0030FC03
   mww phys $CCM_CCGR2 0x0FFFC000
   mww phys $CCM_CCGR3 0x3FF00000
   mww phys $CCM_CCGR4 0x00FFF300
   mww phys $CCM_CCGR5 0x0F0000C3
   mww phys $CCM_CCGR6 0x000003FF
}

proc imx6_cache_init {} {
puts "proc imx6_cache_init ==> begin"

   # asm/arch-mx6/iomux.h
   set MX6_IOMUXC_GPR4         0x020e0010
   set MX6_IOMUXC_GPR6         0x020e0018
   set MX6_IOMUXC_GPR7         0x020e001c
   # asm/arch-mx6/crm_regs.h
   set CCM_CCOSR                      0x020c4060

   # enable AXI cache for VDOA/VPU/IPU */
   mww phys $MX6_IOMUXC_GPR4 0xF00000CF
   mww phys $MX6_IOMUXC_GPR6 0x007F007F
   mww phys $MX6_IOMUXC_GPR7 0x007F007F

   # Setup CCM_CCOSR register as follows:
   #
   # cko1_en = 1     --> CKO1 enabled
   # cko1_div = 111 --> divide by 8
   # cko1_sel = 1011 --> ahb_clk_root
   #
   # This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
   #
   mww phys $CCM_CCOSR 0x000000fb
}

proc imx6d_init {} {
puts "proc imx6d_init ==> begin"

halt
dap apcsw 1

   imx6_clock_init
   imx6d_ddr3_1GB_init
   imx6_cache_init
   mww phys 0x3033012C 0x00000000
   mww phys 0x30330128 0x00000000
   mww phys 0x30860080 0x00000000
}

proc imx7d_init {} {
puts "proc imx7d_init ==> begin"

halt
dap apcsw 1

   mww phys 0x30389800 0x10000000
   mww phys 0x30389880 0x10000001
   mww phys 0x30388000 0x11000000
   mww phys 0x30388080 0x11000000
   mww phys 0x30388100 0x11000000
   mww phys 0x30388800 0x11000000
   mww phys 0x30388880 0x11000000
   mww phys 0x30388900 0x11000000
   mww phys 0x30388980 0x11000000
   mww phys 0x30389000 0x11000001
   mww phys 0x3038a000 0x11000000
   mww phys 0x3038a080 0x11000000
   mww phys 0x3038a100 0x11000000
   mww phys 0x3038a180 0x11000000
   mww phys 0x3038a200 0x11000000
   mww phys 0x3038a280 0x11000000
   mww phys 0x3038a300 0x11000003
   mww phys 0x3038a380 0x11000001
   mww phys 0x3038a400 0x11000001
   mww phys 0x3038a480 0x10000000
   mww phys 0x3038a500 0x11000001
   mww phys 0x3038a580 0x11000001
   mww phys 0x3038a600 0x11000001
   mww phys 0x3038a680 0x11000001
   mww phys 0x3038a700 0x11000000
   mww phys 0x3038a780 0x11000000
   mww phys 0x3038a800 0x11000000
   mww phys 0x3038a880 0x11000000
   mww phys 0x3038a900 0x11000000
   mww phys 0x3038a980 0x11000000
   mww phys 0x3038aa00 0x11000000
   mww phys 0x3038aa80 0x11000000
   mww phys 0x3038ab00 0x11000001
   mww phys 0x3038ab80 0x11000001
   mww phys 0x3038ac00 0x11000001
   mww phys 0x3038ac80 0x11000001
   mww phys 0x3038ad00 0x11000001
   mww phys 0x3038ad80 0x11000001
   mww phys 0x3038ae00 0x11000001
   mww phys 0x3038ae80 0x11000001
   mww phys 0x3038af00 0x11000001
   mww phys 0x3038af80 0x11000002
   mww phys 0x3038b000 0x11000002
   mww phys 0x3038b080 0x11000002
   mww phys 0x3038b100 0x11000002
   mww phys 0x3038b180 0x11000002
   mww phys 0x3038b200 0x11000002
   mww phys 0x3038b280 0x11000002
   mww phys 0x3038b300 0x11000002
   mww phys 0x3038b380 0x11000002
   mww phys 0x3038b400 0x11000002
   mww phys 0x3038b480 0x11000002
   mww phys 0x3038b500 0x11000001
   mww phys 0x3038b580 0x11000001
   mww phys 0x3038b600 0x11000001
   mww phys 0x3038b680 0x11000001
   mww phys 0x3038b700 0x11000001
   mww phys 0x3038b780 0x11000001
   mww phys 0x3038b800 0x11000001
   mww phys 0x3038b880 0x11000001
   mww phys 0x3038b900 0x11000000
   mww phys 0x3038b980 0x11000000
   mww phys 0x3038ba00 0x11000000
   mww phys 0x3038ba80 0x11000000
   mww phys 0x3038bb00 0x11000000
   mww phys 0x3038bb80 0x11000001
   mww phys 0x3038bc00 0x11000000
   mww phys 0x3038bc80 0x11000000
   mww phys 0x3038bd00 0x11000000
   mww phys 0x3038bd80 0x11000000
   mww phys 0x3038be00 0x11000000
#PLL clock change
   mww phys 0x30360070 0x0060302c

   mww phys 0x30384000 0x00000002
   mww phys 0x30384010 0x00000002
   mww phys 0x30384020 0x00000002
   mww phys 0x30384030 0x00000002
   mww phys 0x30384040 0x00000002
   mww phys 0x30384050 0x00000002
   mww phys 0x30384060 0x00000002
   mww phys 0x30384070 0x00000002
   mww phys 0x30384080 0x00000002
   mww phys 0x30384090 0x00000002
   mww phys 0x303840A0 0x00000002
   mww phys 0x303840B0 0x00000002
   mww phys 0x303840C0 0x00000002
   mww phys 0x303840D0 0x00000002
   mww phys 0x303840E0 0x00000002
   mww phys 0x303840F0 0x00000002
   mww phys 0x30384100 0x00000002
   mww phys 0x30384110 0x00000002
   mww phys 0x30384120 0x00000002
   mww phys 0x30384130 0x00000002
   mww phys 0x30384140 0x00000002
   mww phys 0x30384150 0x00000002
   mww phys 0x30384160 0x00000002
   mww phys 0x30384170 0x00000002
   mww phys 0x30384180 0x00000002
   mww phys 0x30384190 0x00000002
   mww phys 0x303841A0 0x00000002
   mww phys 0x303841B0 0x00000002
   mww phys 0x303841C0 0x00000002
   mww phys 0x303841D0 0x00000002
   mww phys 0x303841E0 0x00000002
   mww phys 0x303841F0 0x00000002
   mww phys 0x30384200 0x00000002
   mww phys 0x30384210 0x00000002
   mww phys 0x30384220 0x00000002
   mww phys 0x30384230 0x00000002
   mww phys 0x30384240 0x00000002
   mww phys 0x30384250 0x00000002
   mww phys 0x30384260 0x00000002
   mww phys 0x30384270 0x00000002
   mww phys 0x30384280 0x00000002
   mww phys 0x30384290 0x00000002
   mww phys 0x303842A0 0x00000002
   mww phys 0x303842B0 0x00000002
   mww phys 0x303842C0 0x00000002
   mww phys 0x303842D0 0x00000002
   mww phys 0x303842E0 0x00000002
   mww phys 0x303842F0 0x00000002
   mww phys 0x30384300 0x00000002
   mww phys 0x30384310 0x00000002
   mww phys 0x30384320 0x00000002
   mww phys 0x30384330 0x00000002
   mww phys 0x30384340 0x00000002
   mww phys 0x30384350 0x00000002
   mww phys 0x30384360 0x00000002
   mww phys 0x30384370 0x00000002
   mww phys 0x30384380 0x00000002
   mww phys 0x30384390 0x00000002
   mww phys 0x303843A0 0x00000002
   mww phys 0x303843B0 0x00000002
   mww phys 0x303843C0 0x00000002
   mww phys 0x303843D0 0x00000002
   mww phys 0x303843E0 0x00000002
   mww phys 0x303843F0 0x00000002
   mww phys 0x30384400 0x00000002
   mww phys 0x30384410 0x00000002
   mww phys 0x30384420 0x00000002
   mww phys 0x30384430 0x00000002
   mww phys 0x30384440 0x00000002
   mww phys 0x30384450 0x00000002
   mww phys 0x30384460 0x00000002
   mww phys 0x30384470 0x00000002
   mww phys 0x30384480 0x00000002
   mww phys 0x30384490 0x00000002
   mww phys 0x303844A0 0x00000002
   mww phys 0x303844B0 0x00000002
   mww phys 0x303844C0 0x00000002
   mww phys 0x303844D0 0x00000002
   mww phys 0x303844E0 0x00000002
   mww phys 0x303844F0 0x00000002
   mww phys 0x30384500 0x00000002
   mww phys 0x30384510 0x00000002
   mww phys 0x30384520 0x00000002
   mww phys 0x30384530 0x00000002
   mww phys 0x30384540 0x00000002
   mww phys 0x30384550 0x00000002
   mww phys 0x30384560 0x00000002
   mww phys 0x30384570 0x00000002
   mww phys 0x30384580 0x00000002
   mww phys 0x30384590 0x00000002
   mww phys 0x303845A0 0x00000002
   mww phys 0x303845B0 0x00000002
   mww phys 0x303845C0 0x00000002
   mww phys 0x303845D0 0x00000002
   mww phys 0x303845E0 0x00000002
   mww phys 0x303845F0 0x00000002
   mww phys 0x30384600 0x00000002
   mww phys 0x30384610 0x00000002
   mww phys 0x30384620 0x00000002
   mww phys 0x30384630 0x00000002
   mww phys 0x30384640 0x00000002
   mww phys 0x30384650 0x00000002
   mww phys 0x30384660 0x00000002
   mww phys 0x30384670 0x00000002
   mww phys 0x30384680 0x00000002
   mww phys 0x30384690 0x00000002
   mww phys 0x303846A0 0x00000002
   mww phys 0x303846B0 0x00000002
   mww phys 0x303846C0 0x00000002
   mww phys 0x303846D0 0x00000002
   mww phys 0x303846E0 0x00000002
   mww phys 0x303846F0 0x00000002
   mww phys 0x30384700 0x00000002
   mww phys 0x30384710 0x00000002
   mww phys 0x30384720 0x00000002
   mww phys 0x30384730 0x00000002
   mww phys 0x30384740 0x00000002
   mww phys 0x30384750 0x00000002
   mww phys 0x30384760 0x00000002
   mww phys 0x30384770 0x00000002
   mww phys 0x30384780 0x00000002
   mww phys 0x30384790 0x00000002
   mww phys 0x303847A0 0x00000002
   mww phys 0x303847B0 0x00000002
   mww phys 0x303847C0 0x00000002
   mww phys 0x303847D0 0x00000002
   mww phys 0x303847E0 0x00000002
   mww phys 0x303847F0 0x00000002
   mww phys 0x30384800 0x00000002
   mww phys 0x30384810 0x00000002
   mww phys 0x30384820 0x00000002
   mww phys 0x30384830 0x00000002
   mww phys 0x30384840 0x00000002
   mww phys 0x30384850 0x00000002
   mww phys 0x30384860 0x00000002
   mww phys 0x30384870 0x00000002
   mww phys 0x30384880 0x00000002
   mww phys 0x30384890 0x00000002
   mww phys 0x303848A0 0x00000002
   mww phys 0x303848B0 0x00000002
   mww phys 0x303848C0 0x00000002
   mww phys 0x303848D0 0x00000002
   mww phys 0x303848E0 0x00000002
   mww phys 0x303848F0 0x00000002
   mww phys 0x30384900 0x00000002
   mww phys 0x30384910 0x00000002
   mww phys 0x30384920 0x00000002
   mww phys 0x30384930 0x00000002
   mww phys 0x30384940 0x00000002
   mww phys 0x30384950 0x00000002
   mww phys 0x30384960 0x00000002
   mww phys 0x30384970 0x00000002
   mww phys 0x30384980 0x00000002
   mww phys 0x30384990 0x00000002
   mww phys 0x303849A0 0x00000002
   mww phys 0x303849B0 0x00000002
   mww phys 0x303849C0 0x00000002
   mww phys 0x303849D0 0x00000002
   mww phys 0x303849E0 0x00000002
   mww phys 0x303849F0 0x00000002
   mww phys 0x30384A00 0x00000002
   mww phys 0x30384A10 0x00000002
   mww phys 0x30384A20 0x00000002
   mww phys 0x30384A30 0x00000002
   mww phys 0x30384A40 0x00000002
   mww phys 0x30384A50 0x00000002
   mww phys 0x30384A60 0x00000002
   mww phys 0x30384A70 0x00000002
   mww phys 0x30384A80 0x00000002
   mww phys 0x30384A90 0x00000002
   mww phys 0x30384AA0 0x00000002
   mww phys 0x30384AB0 0x00000002
   mww phys 0x30384AC0 0x00000002
   mww phys 0x30384AD0 0x00000002
   mww phys 0x30384AE0 0x00000002
   mww phys 0x30384AF0 0x00000002
   mww phys 0x30384B00 0x00000002
   mww phys 0x30384B10 0x00000002
   mww phys 0x30384B20 0x00000002
   mww phys 0x30384B30 0x00000002
   mww phys 0x30384B40 0x00000002
   mww phys 0x30384B50 0x00000002
   mww phys 0x30384B60 0x00000002
   mww phys 0x30384B70 0x00000002
   mww phys 0x30384B80 0x00000002
   mww phys 0x30384B90 0x00000002
   mww phys 0x30384BA0 0x00000002
   mww phys 0x30384BB0 0x00000002
   mww phys 0x30384BC0 0x00000002
   mww phys 0x30384BD0 0x00000002
   mww phys 0x30384BE0 0x00000002
   mww phys 0x30384BF0 0x00000002

   mww phys 0x30380800 0x00000002
   mww phys 0x30380810 0x00000002
   mww phys 0x30380820 0x00000002
   mww phys 0x30380830 0x00000002
   mww phys 0x30380840 0x00000002
   mww phys 0x30380850 0x00000002
   mww phys 0x30380860 0x00000002
   mww phys 0x30380870 0x00000002
   mww phys 0x30380880 0x00000002
   mww phys 0x30380890 0x00000002
   mww phys 0x303808A0 0x00000002
   mww phys 0x303808B0 0x00000002
   mww phys 0x303808C0 0x00000002
   mww phys 0x303808D0 0x00000002
   mww phys 0x303808E0 0x00000002
   mww phys 0x303808F0 0x00000002
   mww phys 0x30380900 0x00000002
   mww phys 0x30380910 0x00000002
   mww phys 0x30380920 0x00000002
   mww phys 0x30380930 0x00000002
   mww phys 0x30380940 0x00000002
   mww phys 0x30380950 0x00000002
   mww phys 0x30380960 0x00000002
   mww phys 0x30380970 0x00000002
   mww phys 0x30380980 0x00000002
   mww phys 0x30380990 0x00000002
   mww phys 0x303809A0 0x00000002
   mww phys 0x303809B0 0x00000002
   mww phys 0x303809C0 0x00000002
   mww phys 0x303809D0 0x00000002
   mww phys 0x303809E0 0x00000002
   mww phys 0x303809F0 0x00000002
   mww phys 0x30380A00 0x00000002

#enable ocram epdc
mww phys 0x30340004 0x4F400005

#BOOT_DEVICE_DDR3
   mww phys 0x30391000 0x00000002 #deassert presetn
   mww phys 0x307a0000 0x01040001 #MSTR active ranks is 1 ;burst length is 8 ;ddr3 is enabled
   mww phys 0x307a01a0 0x80400003 #DFIUPD0
   mww phys 0x307a01a4 0x00100020 #DFIUPD1
   mww phys 0x307a01a8 0x80100004 #DFIUPD2
   mww phys 0x307a0064 0x0040005e #RFSHTMG tREFI is 7.8us trfcab is 350ns
   mww phys 0x307a0490 0x00000001 #PCTRL_0 enable port 0
   mww phys 0x307a00d0 0x00020001 #INIT0 pre_cke 100ns
   mww phys 0x307a00d4 0x00010000 #INIT1 dram_rstn_x1024
   mww phys 0x307a00dc 0x09300004 #INIT3 WR=8 CAS=7
   mww phys 0x307a00e0 0x04080000 #INIT4 CWL= 6
   mww phys 0x307a00e4 0x00090004 #INIT5
   mww phys 0x307a00f4 0x0000033f #RANKCTL diff_rank_wr_gap diff_rank_rd_gap set to 3 first ?; max_rank_rd performance
   mww phys 0x307a0100 0x0908120a #DRAMTMG0
   mww phys 0x307a0104 0x0002020e #DRAMTMG1
   mww phys 0x307a0108 0x03040407 #DRAMTMG2
   mww phys 0x307a010c 0x00002006 #DRAMTMG3
   mww phys 0x307a0110 0x04020204 #DRAMTMG4
   mww phys 0x307a0114 0x03030202 #DRAMTMG5
   mww phys 0x307a0120 0x03030803 #DRAMTMG8
   mww phys 0x307a0180 0x00800020 #ZQCTL0 zq_long_nop zq_short_nop
   mww phys 0x307a0190 0x02098204 #DFITMG0
   mww phys 0x307a0194 0x00030303 #DFITMG1
   mww phys 0x307a0200 0x00000016 #ADDRMAP0
   mww phys 0x307a0204 0x00171717 #ADDRMAP1
   mww phys 0x307a0214 0x04040404 #ADDRMAP5
   mww phys 0x307a0218 0x00040404 #ADDRMAP6
   mww phys 0x307a0240 0x06000601 #ODTCFG
   mww phys 0x307a0244 0x00001323 #ODTMAP
   mww phys 0x30391000 0x00000000 #dessert corereset
   mww phys 0x30790000 0x17420f40 #PHY_CON0
   mww phys 0x30790004 0x10210100 #PHY_CON1
   mww phys 0x30790010 0x00060807 #PHY_CON4
   mww phys 0x307900b0 0x1010007e #PHY_CON4
   mww phys 0x3079009c 0x00000d6e #DRVDS_CON0 40ohm except ca 34ohm clk34ohm
   mww phys 0x30790020 0x08080808 #active rising-edge signal
   mww phys 0x30790030 0x08080808 #active rising-edge signal
   mww phys 0x30790050 0x01000010 #active rising-edge signal
   mww phys 0x30790050 0x00000010 #active rising-edge signal

   mww phys 0x307900c0 0x0e407304 #ZQ_CON0
   mww phys 0x307900c0 0x0e447304 #ZQ_CON0
   mww phys 0x307900c0 0x0e447306 #ZQ_CON0
##wait ZQ_CON1 #73 in ds-5 the command time gap is big if your clock is not slow as ds- 5 please add delay here for about 7us
#pause 3s
   mww phys 0x307900c0 0x0e447304 #ZQ_CON0
   mww phys 0x307900c0 0x0e407304 #ZQ_CON0

   mww phys 0x30384130 0x00000000 #disable clock
   mww phys 0x30340020 0x00000178 #assert initial start
   mww phys 0x30384130 0x00000002 #enable clock

   mww phys 0x30790018 0x0000000f #LP_CON0
#wait DDRC_STAT #1 in ds-5 the command time gap is big if your clock is not slow as ds- 5 please add delay here for about 250us
#pause 5s
#wait DDRC_STAT #1 in ds-5 the command time gap is big if your clock is not slow as ds- 5 please add delay here for about 250us
#END_OF_DDR_INIT
   mww phys 0x3033012C 0x00000000
   mww phys 0x30330128 0x00000000
   mww phys 0x30860080 0x00000000
}

proc clear_regs {} {
     puts "proc clear_regs ==> begin"
     reg r1 0
     reg r2 0
     reg r3 0
     reg r4 0
     reg r5 0
     reg r6 0
     reg r7 0
     reg r8 0
     reg r9 0
     reg r10 0
     reg r11 0
     reg r12 0

reg pc 0x10800000

reg cpsr 0x1d3
arm mcr 15 0 15 2 4 0x70000013
}

Re: imx7 openocd tapid and debug base help

fatalfeel — Sat, 10 Sep 2016 05:55:12 GMT

does imx7 have Peripheral Port Memory Remap Register?

want to do

mcr 15 0 15 2 4 0x70000013 -> mcr cp15 0 Rd c15 c2 4 and rd load to 0x70000013

Peripheral Port Memory Remap Register
原文網址：https://read01.com/E84DK4.html

Peripheral Port Memory Remap Register
原文網址：https://read01.com/E84DK4.html

Re: imx7 openocd tapid and debug base help

fatalfeel — Sat, 10 Sep 2016 06:33:47 GMT

arm 外设端口映射__脚本百事通 on sc6410

and

explain 0x70000013 address

select (bin)10011 = 256MB

/////////////////////////////////////////////////////////////////////////////

also same as cortex a8 ARM Information Center

Table 4.2. Memory map for standard peripherals
Peripheral Address range Bus type Region size

Dynamic memory mirror (0x70000000-0x7FFFFFFF)

Re: imx7 openocd tapid and debug base help

fatalfeel — Sat, 10 Sep 2016 09:12:35 GMT

my cfg for imx7 on openocd run ok~~~test ok

thanks for all help~~~~~

http://www.mediafire.com/download/uq29z92sqlmes5a/imx7cfg.tar.gz

Re: imx7 openocd tapid and debug base help

arnoutdiels — Fri, 07 Oct 2016 11:08:52 GMT

Thanks, I have uboot and linux also working with openOCD JTAG debugging. However, has anybody tried dual-core debugging of the IMX7D with openOCD already (e.g. of SMP linux)? I'm guessing a debugbase of 0x80072000, which does detect something that looks like the second core, but a full openOCD config would be nice there.

Now, I can set breakpoints in linux too, but if code is executed on the second core, openocd misses it.

Re: imx7 openocd tapid and debug base help

fatalfeel — Fri, 07 Oct 2016 11:42:04 GMT

I put them in zip

google ->

"OpenOCD + Eclipse + Jtag debug on Uboot & Linux"

imx7 cfg file:
http://www.mediafire.com/file/ytxekpt31oga81t/imx7cfg.zip

Re: imx7 openocd tapid and debug base help

arnoutdiels — Fri, 07 Oct 2016 12:03:10 GMT

I did indeed see the post of fatalfeel, it was pretty neat and detailled. Especially the part regarding the fact that linux resets the hardware breakpoints during init was very useful. However, the post is so low-level and elaborate, explaining patches in openocd itself, its config file, and the linux kernel, that I just did CONFIG_SMP=n at this point. I also don't really see -if- fatalfeel actually has debugging working on the second core or not. Do you know this?

Re: imx7 openocd tapid and debug base help

fatalfeel — Fri, 07 Oct 2016 20:34:36 GMT

I have tired debug for linux and uboot is ok and breakpoint can stop any place
but if want to debug second core only~ need turn openocd cfg to second [Base addresses of cores]

Re: imx7 openocd tapid and debug base help

michalniebieski — Fri, 14 Oct 2016 08:16:16 GMT

Hi.

And what about CortexM4? How to configure OpenOCD?

Re: imx7 openocd tapid and debug base help

fatalfeel — Fri, 14 Oct 2016 09:19:05 GMT

check this post carefully and refer to post of fatalfeel in google

set correct openocd cfg Base addresses of cores

then done and openocd cfg already have m4 example ~~~~

Re: imx7 openocd tapid and debug base help

fatalfeel — Wed, 07 Feb 2018 02:02:06 GMT

https://community.nxp.com/message/984170

do you have i.mx8 debug port and core base address need help

Re: imx7 openocd tapid and debug base help

fatalfeel — Wed, 07 Feb 2018 02:03:49 GMT

do you have i.mx8 debug address
https://community.nxp.com/message/984170