i.MX ProcessorsのトピックRe: parallel lcd data offset

parallel lcd data offset

reuelhaavrahami — Tue, 10 Jan 2017 09:50:29 GMT

We have a parallel display (IPU0_D1) connected as follows:

D0 - to pin J25 (EIM_DA1__IPU1_DISP1_DATA08)........

D15 - to pin E25 (EIM_D27__IPU1_DISP1_DATA23).

Our kernel :Freescale i.MX Release Distro 3.14.52-1.1.1

The framebuffer is setup as RGB565. We can see the clock and sync signals. We can also see the high byte of the RGB signal on EIM_DA1__IPU1_DISP1_DATA08 through to DATA15. The upper byte is all zeros.

Clearly the system is outputting the RGB data on DATA0 to DATA15, but we need it on DATA8 to DATA23.

How do we have the IMX6 (Dual core) shift the RGB on the LCD interface by 8 bits?

It would seem possible to declare a framebuffer format similar to RGB565 with the a different .ofset for red, green and blue. However I am afraid that it might confuse overlay and other work done by the system on the framebuffer.

Re: parallel lcd data offset

igorpadykov — Tue, 10 Jan 2017 10:52:43 GMT

Hi Reuel

for data shifting one can look at sect.37.4.7.5.1 Bus Mapping Unit i.MX6DQ Reference Manual
http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

Best regards
igor
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Re: parallel lcd data offset

reuelhaavrahami — Tue, 10 Jan 2017 11:43:19 GMT

Thanks for the speedy reply. I just love this CPU. However, how do I get this done in the kernel or in the userspace in linux?

Re: parallel lcd data offset

reuelhaavrahami — Wed, 11 Jan 2017 13:19:41 GMT

Perhaps this is a bad hack but I got what I needed by changing the _ipu_init_dc_mappings function in ipu_disp.c (lines867+) in the following manner. (the old values are in comments).

_ipu_dc_map_config(ipu, 3, 0, 12, 0xF8);//_ipu_dc_map_config(ipu, 3, 0, 4, 0xF8);
_ipu_dc_map_config(ipu, 3, 1, 18, 0xFC);//_ipu_dc_map_config(ipu, 3, 1, 10, 0xFC);
_ipu_dc_map_config(ipu, 3, 2, 23, 0xF8);//_ipu_dc_map_config(ipu, 3, 2, 15, 0xF8);