topic Re: PMIC with Custom board in i.MX Processors

PMIC with Custom board

jaiminthakkar — Thu, 17 Nov 2016 13:49:21 GMT

Hi,

We have IMX6 based custom board with PMIC PFUZ100. I am using Android 4.4.3_2.0.0-ga (Boundry Devices) which is based on Freescale BSP.

I have observed that SOC voltages get scaled based on frequency using anatop regulator.

I have following queries regarding PMIC and suspend/resume functionality:

How DDR frequency will get scaled based on CPU frequency? How to check this?
How to find & mention DDR operating points (frequency - voltage table) in dts?

Thanks,

Jaimin Thakkar

Re: PMIC with Custom board

RossMcLuckie — Thu, 17 Nov 2016 17:28:45 GMT

Hi,

The CPU and DRAM are clocked from separate PLL's, so there is no requirement to scale the DRAM frequency with the CPU, however I can't comment specifically on BSP behaviour as I'm not that familiar with it, although I don't think there is much in terms of DRAM frequency scaling, or if there is it is very limited.

Not much more then when running DRAM is at full speed, in low power modes self-refresh mode I believe.

There is a DRAM clock output you could measure on the board, if you have access to it DRAM_SDCLK.

Alternatively, if you have access to CLK1/2 signals you can use the PMU_MISC1 register to output and monitor various system clocks, including the DRAM clock, see the reference manual for further details.

Regards

Ross

Re: PMIC with Custom board

igorpadykov — Thu, 17 Nov 2016 23:43:43 GMT

Depending on activity of the peripheral devices and CPU
loading, the bus frequency driver varies the DDR frequency between 24 MHz and its
maximum frequency. - as described in attached Linux Manual Chapter 25
Dynamic Bus Frequency Driver. For DDR operating points one can check in

linux/arch/arm/mach-imx/busfreq_ddr3.c

Best regards
igor