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    <title>topic IMX6UL Processor GPIO enabling issue in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Processor-GPIO-enabling-issue/m-p/601458#M90444</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;We are using IMX6UL processor in our design, we are facing the issues in&amp;nbsp;GPIO1_IO01(L15), GPIO1_IO02(L14) to enable and disable operation. We measured voltages when configured this pin as a GPIO as Logic '0' = 0.3V, Logic '1' =0.7V instead of 3.3V logic levels. These GPIO signals directly goes to connector and not shared to any other device.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Following are the checking done:&lt;/P&gt;&lt;P&gt;1. In software Device tree is configured fine as per our understanding (we make sure it using point 4).&lt;/P&gt;&lt;P&gt;2. we suspect BGA pins L14, L15 &amp;nbsp;very closer so solder short, ball get damage,Assembly issue. we tried BGA Xray and checked its fine no issue.&lt;/P&gt;&lt;P&gt;3. Our PCB Layout design we confirmed no issue for these 2 pins.&lt;/P&gt;&lt;P&gt;4. we configured&amp;nbsp;&lt;SPAN&gt;GPIO1_IO05,&amp;nbsp;GPIO1_IO06 ,&amp;nbsp;GPIO1_IO07 as GPIO and we are getting Logic '0' = 0.2V and Logic '1' = 3.25V instead of 3.3V. So its fine&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Following are the Queries:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;1. We are using silicon version 1.1 processor which has fixed all errata in Version1.0. If this version 1.1 has any errata issue related to GPIO blocks?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;2. If possible please provide us the Device tree configuration examples which we will cross check in our design?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;3. Please suggest us any prediction from your end based on the deatails which I have mentioned above?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks &amp;amp; Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Rameshkumar&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 21 Mar 2017 07:10:56 GMT</pubDate>
    <dc:creator>ramesh6663</dc:creator>
    <dc:date>2017-03-21T07:10:56Z</dc:date>
    <item>
      <title>IMX6UL Processor GPIO enabling issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Processor-GPIO-enabling-issue/m-p/601458#M90444</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;We are using IMX6UL processor in our design, we are facing the issues in&amp;nbsp;GPIO1_IO01(L15), GPIO1_IO02(L14) to enable and disable operation. We measured voltages when configured this pin as a GPIO as Logic '0' = 0.3V, Logic '1' =0.7V instead of 3.3V logic levels. These GPIO signals directly goes to connector and not shared to any other device.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Following are the checking done:&lt;/P&gt;&lt;P&gt;1. In software Device tree is configured fine as per our understanding (we make sure it using point 4).&lt;/P&gt;&lt;P&gt;2. we suspect BGA pins L14, L15 &amp;nbsp;very closer so solder short, ball get damage,Assembly issue. we tried BGA Xray and checked its fine no issue.&lt;/P&gt;&lt;P&gt;3. Our PCB Layout design we confirmed no issue for these 2 pins.&lt;/P&gt;&lt;P&gt;4. we configured&amp;nbsp;&lt;SPAN&gt;GPIO1_IO05,&amp;nbsp;GPIO1_IO06 ,&amp;nbsp;GPIO1_IO07 as GPIO and we are getting Logic '0' = 0.2V and Logic '1' = 3.25V instead of 3.3V. So its fine&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Following are the Queries:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;1. We are using silicon version 1.1 processor which has fixed all errata in Version1.0. If this version 1.1 has any errata issue related to GPIO blocks?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;2. If possible please provide us the Device tree configuration examples which we will cross check in our design?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;3. Please suggest us any prediction from your end based on the deatails which I have mentioned above?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks &amp;amp; Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Rameshkumar&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Mar 2017 07:10:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Processor-GPIO-enabling-issue/m-p/601458#M90444</guid>
      <dc:creator>ramesh6663</dc:creator>
      <dc:date>2017-03-21T07:10:56Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6UL Processor GPIO enabling issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Processor-GPIO-enabling-issue/m-p/601459#M90445</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN&gt;Rameshkumar&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;if this is one board this may be quality issue and one can try to resolder other chip.&lt;/P&gt;&lt;P&gt;Most simple way is to attach jtag debugger or write from uboot (using mw command) directly to&lt;/P&gt;&lt;P&gt;gpio registers. There are no known processor gpio errata.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Mar 2017 08:29:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Processor-GPIO-enabling-issue/m-p/601459#M90445</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-03-21T08:29:20Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6UL Processor GPIO enabling issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Processor-GPIO-enabling-issue/m-p/601460#M90446</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your quick reply. we will check through JTAG and get beck to you shortly.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; Regards,&lt;/P&gt;&lt;P&gt;Rameshkumar&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Mar 2017 10:05:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Processor-GPIO-enabling-issue/m-p/601460#M90446</guid>
      <dc:creator>ramesh6663</dc:creator>
      <dc:date>2017-03-21T10:05:59Z</dc:date>
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