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    <title>i.MX ProcessorsのトピックRe: Read and Write to DRAM</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Read-and-Write-to-DRAM/m-p/601224#M90349</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;ddr initialized in dcd header in uboot/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg&lt;/P&gt;&lt;P&gt;or similar locations on other boards.&lt;/P&gt;&lt;P&gt;Also it may be useful to check schematic as on some boards reset is performed as&lt;/P&gt;&lt;P&gt;whole board reset when pmic shortly switch off/on (for MMPF0100 using PWRON).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 17 Nov 2016 23:31:49 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-11-17T23:31:49Z</dc:date>
    <item>
      <title>Read and Write to DRAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Read-and-Write-to-DRAM/m-p/601222#M90347</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #333333; background-color: #e1ebf2; font-size: 13px;"&gt;Hi,&lt;/SPAN&gt;&lt;BR style="color: #333333; background-color: #e1ebf2; font-size: 13px;" /&gt;&lt;SPAN style="color: #333333; background-color: #e1ebf2; font-size: 13px;"&gt;I am working on wandboard imx6 dual, I was able to write and read a value to a ram location 0x12000000 using md and mw commands. But once the board was reboot via software the value resets and gets back to the initial value. Why it happens so,is it the actual behavior? Also I would like to know where dram initializatio&lt;/SPAN&gt;&lt;SPAN style="color: #333333; background-color: #e1ebf2; font-size: 13px;"&gt;n takes place.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #333333; background-color: #e1ebf2; font-size: 13px;"&gt;Thanks in advance.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 Nov 2016 13:34:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Read-and-Write-to-DRAM/m-p/601222#M90347</guid>
      <dc:creator>mariyapradeep</dc:creator>
      <dc:date>2016-11-17T13:34:49Z</dc:date>
    </item>
    <item>
      <title>Re: Read and Write to DRAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Read-and-Write-to-DRAM/m-p/601223#M90348</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If the software reboot, generates a hardware reset, via the POR pin, which is likely, then the DRAM controller will be reset and re-initialised and the behaviour you are describing would be expected.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DRAM initialisation is not fixed and up to the user, but the most common, and likely, initialisation is done through the DCD filed at boot time, see the boot chapter in the reference manual for more details -&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/i.mx6qp/i.mx-6dual-processors-dual-core-3d-graphics-hd-video-multimedia-arm-cortex-a9-core:i.MX6D?fpsp=1&amp;amp;tab=Documentation_Tab" title="http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/i.mx6qp/i.mx-6dual-processors-dual-core-3d-graphics-hd-video-multimedia-arm-cortex-a9-core:i.MX6D?fpsp=1&amp;amp;tab=Documentation_Tab"&gt;i.MX 6Dual Processors|Advanced 3D Graphics|NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For more specifics on the wandboard you could try their site and forums -&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://www.wandboard.org/" title="http://www.wandboard.org/"&gt;Wandboard - NXP i.MX6 ARM Cortex-A9 Community Development Board - BLOG&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Ross&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 Nov 2016 17:15:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Read-and-Write-to-DRAM/m-p/601223#M90348</guid>
      <dc:creator>RossMcLuckie</dc:creator>
      <dc:date>2016-11-17T17:15:12Z</dc:date>
    </item>
    <item>
      <title>Re: Read and Write to DRAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Read-and-Write-to-DRAM/m-p/601224#M90349</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;ddr initialized in dcd header in uboot/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg&lt;/P&gt;&lt;P&gt;or similar locations on other boards.&lt;/P&gt;&lt;P&gt;Also it may be useful to check schematic as on some boards reset is performed as&lt;/P&gt;&lt;P&gt;whole board reset when pmic shortly switch off/on (for MMPF0100 using PWRON).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 Nov 2016 23:31:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Read-and-Write-to-DRAM/m-p/601224#M90349</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-11-17T23:31:49Z</dc:date>
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