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    <title>topic PL310, prefetch &amp; errata 765569 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/PL310-prefetch-errata-765569/m-p/597691#M89677</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i.MX6 errata 765569 states that the prefetch offset of the aux control register of the PL310 should be set to any value but 23. By default, this value is 0. Why is NXP's BSP setting this value to 0xf instead of leaving it set to 0 ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Vincent&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 07 Sep 2016 12:10:06 GMT</pubDate>
    <dc:creator>vsiles</dc:creator>
    <dc:date>2016-09-07T12:10:06Z</dc:date>
    <item>
      <title>PL310, prefetch &amp; errata 765569</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PL310-prefetch-errata-765569/m-p/597691#M89677</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i.MX6 errata 765569 states that the prefetch offset of the aux control register of the PL310 should be set to any value but 23. By default, this value is 0. Why is NXP's BSP setting this value to 0xf instead of leaving it set to 0 ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Vincent&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 07 Sep 2016 12:10:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PL310-prefetch-errata-765569/m-p/597691#M89677</guid>
      <dc:creator>vsiles</dc:creator>
      <dc:date>2016-09-07T12:10:06Z</dc:date>
    </item>
    <item>
      <title>Re: PL310, prefetch &amp; errata 765569</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PL310-prefetch-errata-765569/m-p/597692#M89678</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Vincent&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please check&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://ciomrs.dtdns.net:29443/hera/u-boot-imx/commit/5b983bdcbec103a001d30d96b932168f76b712a5" title="https://ciomrs.dtdns.net:29443/hera/u-boot-imx/commit/5b983bdcbec103a001d30d96b932168f76b712a5"&gt;MLK-10496: Check the PL310 version for applying errata (5b983bdc) · Commits · Hera / u-boot-imx · GitLab&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 11 Sep 2016 23:11:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PL310-prefetch-errata-765569/m-p/597692#M89678</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-09-11T23:11:52Z</dc:date>
    </item>
    <item>
      <title>Re: PL310, prefetch &amp; errata 765569</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PL310-prefetch-errata-765569/m-p/597693#M89679</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Great, thank you !&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Sep 2016 07:06:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PL310-prefetch-errata-765569/m-p/597693#M89679</guid>
      <dc:creator>vsiles</dc:creator>
      <dc:date>2016-09-12T07:06:29Z</dc:date>
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