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    <title>i.MX Processors中的主题 Will CSI MIPI need external vsync signal?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Will-CSI-MIPI-need-external-vsync-signal/m-p/597301#M89606</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now I'm working with a mipi camera on imx6 dual lite, after check the RM, I find :&lt;/P&gt;&lt;P&gt; &lt;span class="lia-inline-image-display-wrapper" image-alt="YJ9]ME{VGZ(6JXX4OOMSBO0.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/2282i21D1B06CE9156262/image-size/large?v=v2&amp;amp;px=999" role="button" title="YJ9]ME{VGZ(6JXX4OOMSBO0.jpg" alt="YJ9]ME{VGZ(6JXX4OOMSBO0.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;However, I check through the RM file, and find one vsync pin for CSI0 parallel port but no vsync pin for CSI MIPI.&lt;/P&gt;&lt;P&gt;I&amp;nbsp; wonder if vsync is necessary to make MIPI working ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 15 Aug 2016 11:05:04 GMT</pubDate>
    <dc:creator>ifzhao</dc:creator>
    <dc:date>2016-08-15T11:05:04Z</dc:date>
    <item>
      <title>Will CSI MIPI need external vsync signal?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Will-CSI-MIPI-need-external-vsync-signal/m-p/597301#M89606</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now I'm working with a mipi camera on imx6 dual lite, after check the RM, I find :&lt;/P&gt;&lt;P&gt; &lt;span class="lia-inline-image-display-wrapper" image-alt="YJ9]ME{VGZ(6JXX4OOMSBO0.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/2282i21D1B06CE9156262/image-size/large?v=v2&amp;amp;px=999" role="button" title="YJ9]ME{VGZ(6JXX4OOMSBO0.jpg" alt="YJ9]ME{VGZ(6JXX4OOMSBO0.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;However, I check through the RM file, and find one vsync pin for CSI0 parallel port but no vsync pin for CSI MIPI.&lt;/P&gt;&lt;P&gt;I&amp;nbsp; wonder if vsync is necessary to make MIPI working ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 15 Aug 2016 11:05:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Will-CSI-MIPI-need-external-vsync-signal/m-p/597301#M89606</guid>
      <dc:creator>ifzhao</dc:creator>
      <dc:date>2016-08-15T11:05:04Z</dc:date>
    </item>
    <item>
      <title>Re: Will CSI MIPI need external vsync signal?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Will-CSI-MIPI-need-external-vsync-signal/m-p/597302#M89607</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi If&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;external vsync signal is not needed, as synchs are embedded in mipi&lt;/P&gt;&lt;P&gt;stream, please check&amp;nbsp; Table 19-2. CSI2IPU output signals to IPU&amp;nbsp;&amp;nbsp; vsync,hsync&lt;/P&gt;&lt;P&gt;i.MX6DQ Reference Manual &lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fcache.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fref_manual%2FIMX6DQRM.pdf" rel="nofollow" target="_blank"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 15 Aug 2016 23:49:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Will-CSI-MIPI-need-external-vsync-signal/m-p/597302#M89607</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-08-15T23:49:28Z</dc:date>
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