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    <title>topic Re: MMDC IO mux information for LPDDR3 for i.MX7D in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596220#M89513</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Natali-san,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm sorry for the delay in my response.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Unfortunately, I cannot send NXP schematic for validation board to you, because&amp;nbsp; I think that it is under NDA.&lt;/P&gt;&lt;P&gt;If you need it, I recommend that you contact to Yuri-san.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Yuuki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 08 Mar 2017 12:45:13 GMT</pubDate>
    <dc:creator>yuuki</dc:creator>
    <dc:date>2017-03-08T12:45:13Z</dc:date>
    <item>
      <title>MMDC IO mux information for LPDDR3 for i.MX7D</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596216#M89509</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We want to connect LPDDR3 to i.MX7D.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;We referred to Muxing Options of the reference manual.&lt;BR /&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.nxp.com%2Ffiles%2F32bit%2Fdoc%2Fref_manual%2FIMX7DRM.pdf" rel="nofollow" target="_blank"&gt;http://www.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf&lt;/A&gt;&lt;BR /&gt;&amp;nbsp; - 8.1.1.1 Muxing Options&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, we think that this is the IO name for DDR3.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;May we have MMDC IO mux information for LPDDR3?&lt;BR /&gt;or&lt;BR /&gt;Is there the schematic of LPDDR3 connection which NXP recommends?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Would you confirm whether the table which we made is correct when there is not these information?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Best Reagrds,&lt;BR /&gt;Yuuki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 07 Sep 2016 11:21:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596216#M89509</guid>
      <dc:creator>yuuki</dc:creator>
      <dc:date>2016-09-07T11:21:24Z</dc:date>
    </item>
    <item>
      <title>Re: MMDC IO mux information for LPDDR3 for i.MX7D</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596217#M89510</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear NXP support,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We found a Schematics for WaRP7.&lt;BR /&gt;In WaRP7, i.MX7Solo and LPDDR3 are used.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fwww.element14.com%2Fcommunity%2Fdocs%2FDOC-82961%2Fl%2Fdesign-file-for-warp7-board-schematics-pcb-layout-files" rel="nofollow" target="_blank"&gt;https://www.element14.com/community/docs/DOC-82961/l/design-file-for-warp7-board-schematics-pcb-layout-files&lt;/A&gt;&lt;/P&gt;&lt;P&gt;About connection of LPDDR3, is this the Schematic which NXP recommends?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;May I have advice?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Yuuki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Sep 2016 01:56:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596217#M89510</guid>
      <dc:creator>yuuki</dc:creator>
      <dc:date>2016-09-08T01:56:19Z</dc:date>
    </item>
    <item>
      <title>Re: MMDC IO mux information for LPDDR3 for i.MX7D</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596218#M89511</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Basically it is possible to use the WaRP7 design.&lt;/P&gt;&lt;P&gt;Also I have sent You NXP &lt;SPAN style="color: #51626f; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 15px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; line-height: 25.95px; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; display: inline !important; float: none; background-color: #ffffff;"&gt; schematic for validation board via e-mail. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 15px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; line-height: 25.95px; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; display: inline !important; float: none; background-color: #ffffff;"&gt;Hope it helps.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Sep 2016 04:41:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596218#M89511</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-09-08T04:41:02Z</dc:date>
    </item>
    <item>
      <title>Re: MMDC IO mux information for LPDDR3 for i.MX7D</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596219#M89512</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, I'm new of the community. I also need to connect a LPDDR2 (1Gb x32) to i.MX7D, thus I wish to ask if the warp7 schematic is the recommend one, and/or if you can send a&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;NXP &lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;schematic for validation board.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Thanks.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 07 Mar 2017 11:47:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596219#M89512</guid>
      <dc:creator>federiconatali</dc:creator>
      <dc:date>2017-03-07T11:47:06Z</dc:date>
    </item>
    <item>
      <title>Re: MMDC IO mux information for LPDDR3 for i.MX7D</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596220#M89513</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Natali-san,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm sorry for the delay in my response.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Unfortunately, I cannot send NXP schematic for validation board to you, because&amp;nbsp; I think that it is under NDA.&lt;/P&gt;&lt;P&gt;If you need it, I recommend that you contact to Yuri-san.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Yuuki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Mar 2017 12:45:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596220#M89513</guid>
      <dc:creator>yuuki</dc:creator>
      <dc:date>2017-03-08T12:45:13Z</dc:date>
    </item>
    <item>
      <title>Re: MMDC IO mux information for LPDDR3 for i.MX7D</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596221#M89514</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, Natali!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;As for&amp;nbsp;&amp;nbsp;"if the warp7 schematic is the recommend one" - yes , customers can use it.&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 19 Jul 2018 02:17:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMDC-IO-mux-information-for-LPDDR3-for-i-MX7D/m-p/596221#M89514</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2018-07-19T02:17:51Z</dc:date>
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