<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Issue in DDR calibration values in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Issue-in-DDR-calibration-values/m-p/595603#M89460</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Hrushi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;seems this is described in sect.3.3.1 Identifying Issue on Calibrations&lt;/P&gt;&lt;P&gt;MX6 DRAM Port Application Guide :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There is a chance that there is an error during the calibration, it may&lt;/P&gt;&lt;P&gt;fail to find a valid delay window for some particular bytes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.freescale.com/docs/DOC-101708" title="https://community.freescale.com/docs/DOC-101708"&gt;Freescale i.MX6 DRAM Port Application Guide-DDR3 | NXP Community&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 14 Aug 2016 23:54:34 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-08-14T23:54:34Z</dc:date>
    <item>
      <title>Issue in DDR calibration values</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-in-DDR-calibration-values/m-p/595602#M89459</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have two variants of custom board first one based on i.MX6 solo with 1GB ram and another based on i.MX6 Dualite with 2GB RAM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;When I run the DDR calibration for dualite board I got 12 updated calibration values&lt;/P&gt;&lt;P&gt;but when I run the calibration for Solo board with 1GB ,I am getting only 4 updated calibration values.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So my question is How can I get all the 12 calibration values for solo board?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;we followed I.MX6DQSDL DDR3 Script Aid V0.10 .&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; Regards,&lt;/P&gt;&lt;P&gt;Hrushi&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 13 Aug 2016 05:15:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-in-DDR-calibration-values/m-p/595602#M89459</guid>
      <dc:creator>hrushinale</dc:creator>
      <dc:date>2016-08-13T05:15:04Z</dc:date>
    </item>
    <item>
      <title>Re: Issue in DDR calibration values</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-in-DDR-calibration-values/m-p/595603#M89460</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Hrushi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;seems this is described in sect.3.3.1 Identifying Issue on Calibrations&lt;/P&gt;&lt;P&gt;MX6 DRAM Port Application Guide :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There is a chance that there is an error during the calibration, it may&lt;/P&gt;&lt;P&gt;fail to find a valid delay window for some particular bytes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.freescale.com/docs/DOC-101708" title="https://community.freescale.com/docs/DOC-101708"&gt;Freescale i.MX6 DRAM Port Application Guide-DDR3 | NXP Community&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 14 Aug 2016 23:54:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-in-DDR-calibration-values/m-p/595603#M89460</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-08-14T23:54:34Z</dc:date>
    </item>
    <item>
      <title>Re: Issue in DDR calibration values</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-in-DDR-calibration-values/m-p/595604#M89461</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Igorpadykov,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I run the test multiple times on two different solo boards but still I am getting only four values and not 12.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Kindly guide us regarding this issue.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; Regards,&lt;/P&gt;&lt;P&gt;Hrushi&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 16 Aug 2016 07:28:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-in-DDR-calibration-values/m-p/595604#M89461</guid>
      <dc:creator>hrushinale</dc:creator>
      <dc:date>2016-08-16T07:28:15Z</dc:date>
    </item>
  </channel>
</rss>

