topic Re: Question, i.MX6S DPMI timing in i.MX Processors

Question, i.MX6S DPMI timing

Aemj — Thu, 30 Jun 2016 06:55:43 GMT

Dear team,

I would like to ask about GMPI timing of i.MX6Solo.

In i.MX6Solo datasheet(IMX6SDLIEC, Rev.5), NF16((DS × T -0.67)/18.38) is depicted in Figure 32.

Can I understand that an external NAND chip should set Data within (DS × T -0.67)/18.38 nSec after the falling edge of NAND_RE_B?

My customer believes that setup time should be specified the time before the rising edge of NAND_RE_B written as red line in below.

Thanks,

Miyamoto

Re: Question, i.MX6S DPMI timing

Yuri — Mon, 04 Jul 2016 09:24:33 GMT

Hello,

Since in EDO mode NF16 is different from the definition in non-EDO mode,

it would be better to say about “RE# access time” instead of ”setup time”.

And You are right, this parameter relates to allowable propagation delay between

i.MX6 GPMI NAND_RE_B (LOW) and data from NAND asserted.

Have a great day,
Yuri

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Re: Question, i.MX6S DPMI timing

Aemj — Thu, 28 Jul 2016 06:54:11 GMT

Hello Yuri,

Sorry for may late response.

Let me clarify my understanding as follows:

The read data from NAND should be set after the NF16.

Strictly speaking, it is allowed for the data from NAND to be set at the time of rising edge NAND_RE_B.

e.g.

When DS=3 and T=45.5, then NF16=7.38nSec.

In this situation, the data from NAND should be flowed out after 7.38nSec.

Correct?

Thanks,

Miyamoto

Re: Question, i.MX6S DPMI timing

Yuri — Thu, 28 Jul 2016 07:18:26 GMT

Shortly - Yes.

~Yuri.