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    <title>topic Re: i.MX6UL single ethernet interface in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590171#M89030</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i have a same problem.&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Have you solved the problem since then？&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 14 Aug 2020 07:59:08 GMT</pubDate>
    <dc:creator>quanganhhust</dc:creator>
    <dc:date>2020-08-14T07:59:08Z</dc:date>
    <item>
      <title>i.MX6UL single ethernet interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590166#M89025</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;BR /&gt;Hi, we have a custom design that uses the Dart-6UL (i.mx6ul) from Variscite.&amp;nbsp; The development board has two Ethernet interfaces, and our custom hardware has a single Ethernet interface with a phy connected to the 2nd port.&amp;nbsp; When in u-boot, the link lights work fine, we can ping sites from u-boot, and tftpboot works.&amp;nbsp; When in Linux, the phy registers, but never detects when an ethernet cable is plugged in.&amp;nbsp; Because ethernet works in u-boot, we think the hardware is OK.&amp;nbsp; Could the lack of a phy on eth0 cause the phy on eth1 not to work?&amp;nbsp; I've tried modifying the device tree file, but have not found any changes that work yet.&amp;nbsp; I'm also a bit puzzled by the fec configure in the device tree files (copied below).&amp;nbsp; Why are both phys listed in the fec2 section, instead of one in each section?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;fec1 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-names = "default";&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-mode = "rmii";&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-handle = &amp;lt;&amp;amp;ethphy0&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; status = "okay";&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;fec2 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-names = "default";&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-mode = "rmii";&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-handle = &amp;lt;&amp;amp;ethphy1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; status = "okay";&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; mdio {&lt;/P&gt;&lt;P&gt;&amp;nbsp; #address-cells = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; #size-cells = &amp;lt;0&amp;gt;;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; ethphy0: ethernet-phy@2 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "ethernet-phy-ieee802.3-c22";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; ethphy1: ethernet-phy@1 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "ethernet-phy-ieee802.3-c22";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Jun 2016 18:41:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590166#M89025</guid>
      <dc:creator>cbrake</dc:creator>
      <dc:date>2016-06-29T18:41:25Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6UL single ethernet interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590167#M89026</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I was hoping something like this would work, but with this change, neither port on the dev board works:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I do notice a difference in the phy detection -- before this change, I get:&lt;/P&gt;&lt;P&gt;fec 2188000.ethernet eth1: Freescale FEC PHY driver [Micrel KSZ8081 or KSZ8091] (mii_bus:phy_addr=20b4000.ethernet:01, irq=-1)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;After this change, I get:&lt;/P&gt;&lt;P&gt;fec 2188000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=2188000.ethernet:01, irq=-1)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Notice, the Phy changed from Micrel KSZ8081 to Generic PHY.&lt;/P&gt;&lt;P&gt;With the original DT configured for two ports, I get:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #4d4d4d; font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif; font-size: 14px;"&gt;fec 20b4000.ethernet eth0: registered PHC device 0&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #4d4d4d; font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif; font-size: 14px;"&gt;fec 2188000.ethernet eth1: registered PHC device 1&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #4d4d4d; font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif; font-size: 14px;"&gt;fec 20b4000.ethernet eth0: Freescale FEC PHY driver [Micrel KSZ8081 or KSZ8091] (mii_bus:phy_addr=20b4000.ethernet:03, irq=-1)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #4d4d4d; font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif; font-size: 14px;"&gt;fec 2188000.ethernet eth1: Freescale FEC PHY driver [Micrel KSZ8081 or KSZ8091] (mii_bus:phy_addr=20b4000.ethernet:01, irq=-1)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #4d4d4d; font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif; font-size: 14px;"&gt;Its interesting that both phys are mapped to controller at 20b4000.&amp;nbsp; Perhaps this is how the mdio bus is wired internally or something ...&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Below is a change to attempt to disable one port.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;fec1 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-names = "default";&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-mode = "rmii";&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-reset-gpios=&amp;lt;&amp;amp;gpio5 0 1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-reset-duration=&amp;lt;100&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-handle = &amp;lt;&amp;amp;ethphy0&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; status = "okay";&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; mdio {&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; ethphy0: ethernet-phy@1 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "ethernet-phy-ieee802.3-c22";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/*&lt;/P&gt;&lt;P&gt;&amp;amp;fec2 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-names = "default";&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-mode = "rmii";&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-handle = &amp;lt;&amp;amp;ethphy1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-reset-gpios=&amp;lt;&amp;amp;gpio1 10 1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-reset-duration=&amp;lt;100&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; status = "okay";&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; mdio {&lt;/P&gt;&lt;P&gt;&amp;nbsp; #address-cells = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; #size-cells = &amp;lt;0&amp;gt;;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; ethphy0: ethernet-phy@1 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "ethernet-phy-ieee802.3-c22";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; ethphy1: ethernet-phy@3 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "ethernet-phy-ieee802.3-c22";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;3&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;P&gt;*/&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Jun 2016 19:00:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590167#M89026</guid>
      <dc:creator>cbrake</dc:creator>
      <dc:date>2016-06-29T19:00:39Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6UL single ethernet interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590168#M89027</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;With this DT change, I was able to disable the eth0 phy, and eth1 worked fine on the dev board.&amp;nbsp; However it still does not work on our custom hardware with no phy on eth0.&amp;nbsp; Both boards output the following kernel messages:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;root@imx6ul-var-dart:~# dmesg | grep fec&lt;/P&gt;&lt;P&gt;libphy: fec_enet_mii_bus: probed&lt;/P&gt;&lt;P&gt;fec 20b4000.ethernet eth0: registered PHC device 0&lt;/P&gt;&lt;P&gt;fec 2188000.ethernet eth1: registered PHC device 1&lt;/P&gt;&lt;P&gt;CLIFF: fec_enet_mii_probe&lt;/P&gt;&lt;P&gt;fec 20b4000.ethernet eth0: no PHY, assuming direct connection to switch&lt;/P&gt;&lt;P&gt;fec 20b4000.ethernet eth0: could not attach to PHY&lt;/P&gt;&lt;P&gt;CLIFF: fec_enet_mii_probe&lt;/P&gt;&lt;P&gt;fec 20b4000.ethernet eth0: no PHY, assuming direct connection to switch&lt;/P&gt;&lt;P&gt;fec 20b4000.ethernet eth0: could not attach to PHY&lt;/P&gt;&lt;P&gt;CLIFF: fec_enet_mii_probe&lt;/P&gt;&lt;P&gt;fec 2188000.ethernet eth1: Freescale FEC PHY driver [Micrel KSZ8081 or KSZ8091] (mii_bus:phy_addr=20b4000.ethernet:01, irq=-1)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;fec1 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-names = "default";&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-mode = "rmii";&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-reset-gpios=&amp;lt;&amp;amp;gpio5 0 1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-reset-duration=&amp;lt;100&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-handle = &amp;lt;&amp;amp;ethphy0&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; status = "okay";&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;fec2 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-names = "default";&lt;/P&gt;&lt;P&gt;&amp;nbsp; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet2&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; //phy-mode = "rmii";&lt;/P&gt;&lt;P&gt;&amp;nbsp; //phy-handle = &amp;lt;&amp;amp;ethphy1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-reset-gpios=&amp;lt;&amp;amp;gpio1 10 1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; phy-reset-duration=&amp;lt;100&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; status = "okay";&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; mdio {&lt;/P&gt;&lt;P&gt;&amp;nbsp; #address-cells = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; #size-cells = &amp;lt;0&amp;gt;;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; ethphy0: ethernet-phy@1 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "ethernet-phy-ieee802.3-c22";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/*&lt;/P&gt;&lt;P&gt;&amp;nbsp; ethphy1: ethernet-phy@3 {&lt;/P&gt;&lt;P&gt;&amp;nbsp; compatible = "ethernet-phy-ieee802.3-c22";&lt;/P&gt;&lt;P&gt;&amp;nbsp; reg = &amp;lt;3&amp;gt;;&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;*/&lt;/P&gt;&lt;P&gt;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Jun 2016 19:29:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590168#M89027</guid>
      <dc:creator>cbrake</dc:creator>
      <dc:date>2016-06-29T19:29:43Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6UL single ethernet interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590169#M89028</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;This appears to be an issue with the first two Variscite modules -- we tried two more, and they work fine with no DT modifications.&amp;nbsp; It is still a puzzle to me why the Ethernet port works fine in u-boot, but fails in Linux.&amp;nbsp; We did program the i.MX6UL fuses using the following command to boot from SD on our custom board:&lt;/P&gt;&lt;P&gt;fuse prog 0 5 0x40&lt;/P&gt;&lt;P&gt;But, did not seem to change anything related to Ethernet on boards 3 &amp;amp; 4.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 01 Jul 2016 19:52:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590169#M89028</guid>
      <dc:creator>cbrake</dc:creator>
      <dc:date>2016-07-01T19:52:58Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6UL single ethernet interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590170#M89029</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Have you solved the problem since then？I had a similar problem on the imx6ull&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Looking forward to your reply.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Jun 2020 01:08:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590170#M89029</guid>
      <dc:creator>940849422</dc:creator>
      <dc:date>2020-06-04T01:08:50Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6UL single ethernet interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590171#M89030</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i have a same problem.&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Have you solved the problem since then？&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 14 Aug 2020 07:59:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6UL-single-ethernet-interface/m-p/590171#M89030</guid>
      <dc:creator>quanganhhust</dc:creator>
      <dc:date>2020-08-14T07:59:08Z</dc:date>
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