topic Re: ECSPI clk polarity issue IMX6dq in i.MX Processors

ECSPI clk polarity issue IMX6dq

khaledali — Sun, 04 Sep 2016 14:00:12 GMT

Hi all,
I'm facing an awkward problem with ecspi. I tried to change the polarity of the clk and read the configuration register to be sure.
and i found that the polarity bit in my channel has been changed but without any effect.

are there any other bits to check?

Re: ECSPI clk polarity issue IMX6dq

igorpadykov — Sun, 04 Sep 2016 23:30:37 GMT

Hi Khaled

please try to reset block and follow sect.21.5 Initialization

i.MX6DQ Reference Manual (rev.0 2/2016)
http://cache.nxp.com/files/soft_dev_tools/doc/support_info/iMX6DQPRM.pdf

Best regards
igor
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Re: ECSPI clk polarity issue IMX6dq

khaledali — Mon, 05 Sep 2016 07:49:54 GMT

Thanks igor for you answer.
I tried to do the same initialization but if i tried to change the polarity the bit inside the
configuration register changed but the the idle state of the clk still low.

so this is my configurations I'm using the SDK driver after little modifications please see the configuration function
I'm using ecspi instance 2
with param variable :
.channel = 1.
.mode = 1
.ss_pol = 0
.sclk_pol = 1
.sclk_pha = 1
.pre_div = 14
.post_div = 2

The configuration function :

int ecspi_configure(dev_ecspi_e instance, const param_ecspi_t * param)
{
// Reset eCSPI controller
HW_ECSPI_CONREG(instance).B.EN = 0;

// Enable the clock*
clock_gating_config(REGS_ECSPI_BASE(instance), CLOCK_ON);

//Enable the ECSPI*
HW_ECSPI_CONREG(instance).B.EN = 1;

// Configure IO signals
ecspi_iomux_config(instance);

// Setup chip select
HW_ECSPI_CONREG(instance).B.CHANNEL_SELECT = param->channel;

// Setup mode
uint32_t channelMask = 1 << param->channel;
uint32_t value = HW_ECSPI_CONREG(instance).B.CHANNEL_MODE;
BW_ECSPI_CONREG_CHANNEL_MODE(instance, param->mode ? (value | channelMask) : (value & ~channelMask));

// Setup pre & post clock divider
HW_ECSPI_CONREG(instance).B.PRE_DIVIDER = (param->pre_div == 0) ? 0 : (param->pre_div - 1);
HW_ECSPI_CONREG(instance).B.POST_DIVIDER = param->post_div;

// Setup SCLK_PHA, SCLK_POL, SS_POL
value = HW_ECSPI_CONFIGREG(instance).B.SCLK_PHA;
HW_ECSPI_CONFIGREG(instance).B.SCLK_PHA = param->sclk_pha ? (value | channelMask) : (value & ~channelMask);

value = HW_ECSPI_CONFIGREG(instance).B.SCLK_POL;
HW_ECSPI_CONFIGREG(instance).B.SCLK_POL = param->sclk_pol ? (value | channelMask) : (value & ~channelMask);

value = HW_ECSPI_CONFIGREG(instance).B.SS_POL;
HW_ECSPI_CONFIGREG(instance).B.SS_POL = param->ss_pol ? (value | channelMask) : (value & ~channelMask);

HW_ECSPI_CONFIGREG(instance).B.SS_CTL |= channelMask;

return SUCCESS;
}

Re: ECSPI clk polarity issue IMX6dq

khaledali — Mon, 05 Sep 2016 08:54:12 GMT

thanks igor
i have just figure out the problem in the configuration
in the SCLK_CTL bits in the configuration register