i.MX ProcessorsのトピックQuestion, i.MX6SL internal PLL use

Question, i.MX6SL internal PLL use

Aemj — Mon, 18 Jul 2016 08:59:14 GMT

Dear team,

My customer is trying to reduce the power dissipation of i.MX6SL by configuring CCM_ANALOG_PLL_SYS/BYPASS[16Bit] as the situation demands of their application.

When they set the internal PLL of i.MX6SL into bypassed, the power dissipation can be reduced.

The issue is;

When they switch the CCM_ANALOG_PLL_SYS/BYPASS[16Bit], memory access error (data abort or pre-fetch abort) could occur on their board.

They believes that the issue is caused because the switching the bit can affect the DDR clock.

Correct?

If you have any ideas to avoid such problems, please let me know.

Thanks,

Miyamoto

Re: Question, i.MX6SL internal PLL use

igorpadykov — Tue, 19 Jul 2016 00:28:02 GMT

Hi Miyamoto

right, switching pll2 may affect ddr clock. It may be useful to

check example of running ddr at low frequency in

linux/arch/arm/mach-imx/imx6sl_low_power_idle.S

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-imx/imx6sl_low_power_idle.S?h=imx_4.1.15_1.0.0_ga

Best regards

igor

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Re: Question, i.MX6SL internal PLL use

Aemj — Fri, 12 Aug 2016 01:59:55 GMT

Hi Igor,

Sorry for my late reply.

My customer is still facing this issue.

The user program is located on the internal RAM of i.MX6SL, and the software is to change the PLL2 settings into bypass.

After the settings have done, the pre-fetching abort or data abort can occur on their board.

They saw the data in RAM have been changed, and they think the abort can occur due to the change of data in internal RAM.

Please show me the correct sequence of the PLL2 setting change for bypassing PLL.

The bypass setting is very important for them to reduce power consumption.

Best Regards,

Miyamoto

Re: Question, i.MX6SL internal PLL use

igorpadykov — Fri, 12 Aug 2016 05:21:37 GMT

Hi Miyamoto

it may be useful to look at EB790

http://cache.nxp.com/files/32bit/doc/eng_bulletin/EB790.pdf

If this will not help and since this is custom board, suggest to elevate issue using

local fae channel for obtaining additional support.

Best regards

igor

Re: Question, i.MX6SL internal PLL use

Aemj — Tue, 23 Aug 2016 00:47:14 GMT

Hi Igor,

My customer have checked that the same issue had occurred on NXP/EVK board as well. For the reproducing the issue, they made IAR/EW’s project file.

The compiled image is to be downloaded via JTAG from IAR/EW.

If you can reproduce the issue with IAR environment, I can send the project file to you.

If you need it, please let me know the way to transfer the file. The size of the file is about 33MB.

Can you reproduce the issue with the project file?

The following is the quick explanation of the source code.

In wait_mode.c source file, mxc_cpu_lp_set_os_in() and mxc_cpu_lp_set_os_out() functions are called periodically.

In those functions, BYPASS bit of CCM_ANALOG_PLL_SYSn(PLL2’s Bypass bit) is to set/clear.

After reading LinuxBSP code and documents you showed us, they do only set/clear the BYPASS bit for switching bypass/non-bypass.

In the document EB790(configuring PFD), it is said that PLL should be powered-down when the PFD needs to be re-configured. But the customer does not do the PLL power-down because they need to switch PLL2’s bypass mode for their application.

If other sequence than switching the BYPASS bit is needed for switching bypass mode, please let me know.

Thanks,

Miyamoto

Re: Question, i.MX6SL internal PLL use

igorpadykov — Tue, 23 Aug 2016 01:50:48 GMT

Hi Miyamoto

nxp only supports linux for i.MX6SL, so

please try to reproduce it with i.MX6SL EVK Demo Images found on

i.MX 6 Series Software and Development Tool|NXP

Please try latest L4.1.15 release.

For other environments like baremetal, IAR/EW e.t.c. please

try more extended support level like NXP Professional Services

or elevate issue using local fae channel.

Best regards

igor

Re: Question, i.MX6SL internal PLL use

Aemj — Fri, 02 Sep 2016 02:43:10 GMT

Hi Igor,

Thanks so much for your support.

After checking your LinuxBSP source code, the customer understand that the followings are needed for changing PLL2 bypass setting.

The code should be located on OCRAM.
Before executing the code, SDRAM should be in self-reflash mode.
Because SDRAM is in self-reflash-mode, the software should not use stack.

And the customer checked that the issue does not occur on their code which includes the above.

The point is;

Before the changing of PLL2 bypass setting, DDR should be in self-reflesh mode.

The customer wants to be sure that the above is reasonable in terms of technical viewpoint.

Could you give us your comment on that?

Thanks,

Miyamoto

Re: Question, i.MX6SL internal PLL use

igorpadykov — Fri, 02 Sep 2016 05:00:19 GMT

Hi Miyamoto

I think this is correct sequence.

Best regards

igor