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    <title>topic Re:   Multi-core Timer Interrupt in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Multi-core-Timer-Interrupt/m-p/578563#M88215</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Khaled&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please look at link below with epit example&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.freescale.com/docs/DOC-95578" title="https://community.freescale.com/docs/DOC-95578"&gt;i.MX6 AVB Demo Implementation | NXP Community&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 11 Aug 2016 00:07:15 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-08-11T00:07:15Z</dc:date>
    <item>
      <title>Multi-core Timer Interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Multi-core-Timer-Interrupt/m-p/578562#M88214</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;how can ! i make the EPIT timer interrupts the 4 cores &lt;BR /&gt;i'm using the imx6dq and the SDK &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Aug 2016 08:52:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Multi-core-Timer-Interrupt/m-p/578562#M88214</guid>
      <dc:creator>khaledali</dc:creator>
      <dc:date>2016-08-08T08:52:43Z</dc:date>
    </item>
    <item>
      <title>Re:   Multi-core Timer Interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Multi-core-Timer-Interrupt/m-p/578563#M88215</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Khaled&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please look at link below with epit example&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.freescale.com/docs/DOC-95578" title="https://community.freescale.com/docs/DOC-95578"&gt;i.MX6 AVB Demo Implementation | NXP Community&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 11 Aug 2016 00:07:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Multi-core-Timer-Interrupt/m-p/578563#M88215</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-08-11T00:07:15Z</dc:date>
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