topic i.MX6UL: CCM_CLKO2 arm_clk_root on SD1_DATA2 pad in i.MX Processors

i.MX6UL: CCM_CLKO2 arm_clk_root on SD1_DATA2 pad

michaelschell — Fri, 15 Jul 2016 20:44:55 GMT

Hello, we are using the i.MX6UL platform and I need to observe the arm_root_clk on CCM_CLKO2 on the SD1_DATA2 pad as detailed in the RM. We are doing this because we need a visual representation of our operating frequency. My settings are as follows:

CCM Clock Output Source Register (CCM_CCOSR) (0x20C_4060h)

- set to value 0x018a0100

- this selects arm_root_clk for CLKO2 with divider of 5

SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3) (0x20E_01D0h)

- set to value 0x00000006

- this selects ALT6 mode for CCM_CLKO2

SW_PAD_CTL_PAD_SD1_DATA3 SW PAD Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3) (0x20E_045Ch)

- set to value 0x0001F0D9

- this sets 200Mhz max pad freq

With these setting I am unable to see a clock on SD1_DATA2. If I change CCM_CCOSR to 0x010e0000 I will see the 24Mhz osc_clk correctly. I can also seem to see all other CLKO2 clocks - just not the one I need.

Is there something further I need to do to view the arm_clk_root clock?

Re: i.MX6UL: CCM_CLKO2 arm_clk_root on SD1_DATA2 pad

igorpadykov — Sat, 16 Jul 2016 01:35:14 GMT

Hi michaelschell

unfortunately i.MX6UL has not selection CLKO2_SEL= 01010 arm_clk_root,

it is reserved :

i.MX6UL Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6ULRM.pdf

Best regards

igor

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Re: i.MX6UL: CCM_CLKO2 arm_clk_root on SD1_DATA2 pad

michaelschell — Sat, 16 Jul 2016 11:59:13 GMT

Thanks so much igor. Im clearly using the wrong version of the i.MX6UL reference manual. Mine does not show that value (01010) as reserved but instead specifies it for arm_clk_root. Ill move forward with this version of the RM. To your knowledge then, for the i.MX6UL, is there no way to export the arm clock (cpu clock rate) off chip?