i.MX Processors中的主题 Re: i.MX6 RGMII pads internal register settings.

i.MX6 RGMII pads internal register settings.

norishinozaki — Fri, 15 Jul 2016 04:25:22 GMT

Hello Champs,

I'd like to decide internal PUS, PUE and/or PKE and the values.

In the HDGW 9.5.1.2 RGMII discusses as follow.

“Drive strength Controlled by bits [5:3] (DSE) of the following registers

in IOMUXC (IOMUX controller):

IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC

IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL

IOMUXC_SW_PAD_CTL_PAD_RGMII_TDx (4 registers)

IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC

IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL

IOMUXC_SW_PAD_CTL_PAD_RGMII_RDx (4 registers)”

However the IBIS currently supports only the 2.5 V option.

We are using 1.5V.

Could you advice how to decide PUS, PUE and/or PKE and the values?

BR,
N.S.

Re: i.MX6 RGMII pads internal register settings.

Yuri — Fri, 15 Jul 2016 06:48:44 GMT

Hello,

hope, the following app note helps.

"Influence of Pin Setting on System Function and Performance"

http://cache.freescale.com/files/32bit/doc/app_note/AN5078.pdf

Have a great day,
Yuri

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Re: i.MX6 RGMII pads internal register settings.

norishinozaki — Fri, 15 Jul 2016 08:18:54 GMT

Hello Yuri,

Thanks!

In the Sabre SD u-boot, RGMII pads are all 0x0001b0b0

HYS -> 1 : ENABLED

PUS -> 10 : 100K_PU ( the default is 00: 100K_PD in Reference Manual)

PUE -> 1 : PULL

PKE -> 1 : ENABLED

DSE -> 110 : 37_OHM

Besides resistance values, should we enable pull-up and Keeper for all i.MX6Q with RGMII?

Have you heard some one used different settings from the above settings?

Best regards,

N.S.

Re: i.MX6 RGMII pads internal register settings.

Yuri — Fri, 15 Jul 2016 08:28:45 GMT

Hi,

Enabling pull-up and keeper is reasonable to avoid issues with unstable state

of pin, say during suspend / resume.

Regards,

Yuri.

Re: i.MX6 RGMII pads internal register settings.

norishinozaki — Fri, 15 Jul 2016 08:33:39 GMT

Yuri,

Thanks!

BR,

N.S.