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    <title>topic Re: iMX6UL PSRAM launching problem. in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX6UL-PSRAM-launching-problem/m-p/546417#M85837</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please refer chapter 22.7 of i.MX 6UltraLite Applications Processor Reference Manual regarding to PSRAM initialization.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;/P&gt;&lt;P&gt;Victor&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 23 Aug 2016 07:45:49 GMT</pubDate>
    <dc:creator>b36401</dc:creator>
    <dc:date>2016-08-23T07:45:49Z</dc:date>
    <item>
      <title>iMX6UL PSRAM launching problem.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6UL-PSRAM-launching-problem/m-p/546416#M85836</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;Hi,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;I am currently trying to force PSRAM to work. The PSRAM chip that I have on board is ISSI &lt;STRONG&gt;IS66WVC2M16ALL&lt;/STRONG&gt;&amp;nbsp; which is compatible with Micron Cellular RAM 1.5 spec.&lt;BR /&gt;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp; I am using EIM driver setup to run this memory chip.&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp; I configured Linux device tree as follow:&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp; pinctrl_weim: weimgrp {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; fsl,pins = &amp;lt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_DATA00__EIM_AD00&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_DATA01__EIM_AD01&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_DATA02__EIM_AD02&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_DATA03__EIM_AD03&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_DATA04__EIM_AD04&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_DATA05__EIM_AD05&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_DATA06__EIM_AD06&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_DATA07__EIM_AD07&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_DATA00__EIM_AD08&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_DATA01__EIM_AD09&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_DATA02__EIM_AD10&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_DATA03__EIM_AD11&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_DATA04__EIM_AD12&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_DATA05__EIM_AD13&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_DATA06__EIM_AD14&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_DATA07__EIM_AD15&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_CLE__EIM_ADDR16&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_ALE__EIM_ADDR17&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0xb0b1&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_MCLK__EIM_CS0_B&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_PIXCLK__EIM_OE&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_VSYNC__EIM_RW&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_CSI_HSYNC__EIM_LBA_B&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_RE_B__EIM_EB_B00&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_WE_B__EIM_EB_B01&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_WP_B__EIM_BCLK&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_NAND_DQS__EIM_WAIT&amp;nbsp; 0xb060&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_ENET1_RX_ER__EIM_CRE&amp;nbsp; 0xb0b1&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x1b0b1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; };&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp; &amp;amp;weim {&lt;BR /&gt;&amp;nbsp;&amp;nbsp; #address-cells = &amp;lt;2&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; #size-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; ranges = &amp;lt;0x0 0x0 0x50000000 0x400000&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; fsl,weim-cs-gpr = &amp;lt;&amp;amp;gpr&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; bank-width = &amp;lt;2&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; pinctrl-names = "default";&lt;BR /&gt;&amp;nbsp;&amp;nbsp; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_weim&amp;gt;;&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp; status = "okay";&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp; psram: psram@50000000 {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; compatible = "mmio-sram";&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; reg = &amp;lt;0x0 0x0 0x400000&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; fsl,weim-cs-timing = &amp;lt;&lt;STRONG&gt;0x403104b1 0x00000000 0x0b010000&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000008 0x0b040040 0x00000000&lt;/STRONG&gt;&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; };&lt;BR /&gt;&amp;nbsp; };&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp; The EIM driver (imx-weim.c) is set to be as given in iMX6UL RM point 21.7.3.1(Micron PSRAM Asynchronus Mode Configuration) for 16 bit memory.&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp; After the system start I have the following:&lt;BR /&gt;&amp;nbsp; cat /proc/iomem&lt;BR /&gt;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp; ...&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp; 50000000-503fffff : 50000000.psram&lt;BR /&gt;&amp;nbsp; ...&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp; Which show me that psram is registered in the system.&lt;BR /&gt;&amp;nbsp; But when I try to access the memory by&lt;BR /&gt;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp; devmem2 0x50000000&lt;BR /&gt;&amp;nbsp; I receive that&lt;BR /&gt;&amp;nbsp; /dev/mem opened.&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp; and the system is going to hang up.&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp; I suppose that I have wrong registers values here :&lt;BR /&gt;&amp;nbsp; &lt;STRONG&gt;fsl,weim-cs-timing = &amp;lt;0x403104b1 0x00000000 0x0b010000&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000008 0x0b040040 0x00000000&amp;gt;;&lt;/STRONG&gt;&lt;BR /&gt; &lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt; &lt;STRONG&gt;Has anyone successfully run this particular model of PSRAM chip with IMX6 and can provide the accurate timings please?&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;I am wondering as well if the problem is not caused by not&lt;/SPAN&gt;&lt;SPAN style="font-size: 10pt;"&gt; connected on my board PSRAM pins &lt;STRONG&gt;A19 and A20 to the IMX6&lt;/STRONG&gt;? As pin A19 can be used to set PSRAM control registers.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;But in the PSRAM documentation there is as well 'software way' of setting those control registers showed - so I doubt whether A19 is important here?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;Krzysztof Lukaszewicz&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 22 Aug 2016 13:21:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6UL-PSRAM-launching-problem/m-p/546416#M85836</guid>
      <dc:creator>krzysztoflukasz</dc:creator>
      <dc:date>2016-08-22T13:21:35Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6UL PSRAM launching problem.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6UL-PSRAM-launching-problem/m-p/546417#M85837</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please refer chapter 22.7 of i.MX 6UltraLite Applications Processor Reference Manual regarding to PSRAM initialization.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;/P&gt;&lt;P&gt;Victor&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 23 Aug 2016 07:45:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6UL-PSRAM-launching-problem/m-p/546417#M85837</guid>
      <dc:creator>b36401</dc:creator>
      <dc:date>2016-08-23T07:45:49Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6UL PSRAM launching problem.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6UL-PSRAM-launching-problem/m-p/546418#M85838</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi，Victor:&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; I can't find the&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;chapter 22.7 in the&amp;nbsp;&lt;SPAN&gt;i.MX 6UltraLite Applications Processor Reference Manual,and now I also&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;have the problem of PSRAM.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 08 Jan 2019 13:23:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6UL-PSRAM-launching-problem/m-p/546418#M85838</guid>
      <dc:creator>刘卫强刘</dc:creator>
      <dc:date>2019-01-08T13:23:13Z</dc:date>
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