<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic iMX7D :  Connecting to LPDDR2 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Connecting-to-LPDDR2/m-p/545346#M85753</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear community,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; We have been developing our product with iMX7D.&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; I hope to connect a LPDDR2 to the iMX7D.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In Reference Manual IMX6SDLRM Rev. 2 , 45.4.5 LPDDR2 and DDR3 pin mux mapping,&lt;BR /&gt;it is described that the LPDDR2 and DRAM pin mux mapping for iMX6.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;But , in the iMX7D Reference Manual the LPDDR2 and DRAM pin mux mapping is not defined.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Question]&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Could you teach me the LPDDR2 pin mux mapping for&amp;nbsp; iMX7 ?&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Or ,as DRAM I/O pad name and LPDDR2 functionality is consistent ,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Is the pin mux mapping unnecessary ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards, &lt;BR /&gt;Koichi Sakagami &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 22 Aug 2016 09:37:14 GMT</pubDate>
    <dc:creator>koichisakagami</dc:creator>
    <dc:date>2016-08-22T09:37:14Z</dc:date>
    <item>
      <title>iMX7D :  Connecting to LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Connecting-to-LPDDR2/m-p/545346#M85753</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear community,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; We have been developing our product with iMX7D.&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; I hope to connect a LPDDR2 to the iMX7D.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In Reference Manual IMX6SDLRM Rev. 2 , 45.4.5 LPDDR2 and DDR3 pin mux mapping,&lt;BR /&gt;it is described that the LPDDR2 and DRAM pin mux mapping for iMX6.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;But , in the iMX7D Reference Manual the LPDDR2 and DRAM pin mux mapping is not defined.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Question]&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Could you teach me the LPDDR2 pin mux mapping for&amp;nbsp; iMX7 ?&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Or ,as DRAM I/O pad name and LPDDR2 functionality is consistent ,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Is the pin mux mapping unnecessary ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards, &lt;BR /&gt;Koichi Sakagami &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 22 Aug 2016 09:37:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Connecting-to-LPDDR2/m-p/545346#M85753</guid>
      <dc:creator>koichisakagami</dc:creator>
      <dc:date>2016-08-22T09:37:14Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7D :  Connecting to LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Connecting-to-LPDDR2/m-p/545347#M85754</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The signal mapping of the i.MX7D DDR bus interface is equal for both DDR3 and LPDDR2 memories, so, no separate pin mapping is required for the LPDDR2 memory.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 30 Aug 2016 09:24:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Connecting-to-LPDDR2/m-p/545347#M85754</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-08-30T09:24:44Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7D :  Connecting to LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Connecting-to-LPDDR2/m-p/545348#M85755</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Artur san,&lt;BR /&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I got it.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Is the signal mapping of the i.MX7D DDR bus interface&amp;nbsp; equal for LPDDR3 memory ,too ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards, &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Koichi Sakagami&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 31 Aug 2016 05:40:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Connecting-to-LPDDR2/m-p/545348#M85755</guid>
      <dc:creator>koichisakagami</dc:creator>
      <dc:date>2016-08-31T05:40:45Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7D :  Connecting to LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Connecting-to-LPDDR2/m-p/545349#M85756</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 31 Aug 2016 07:18:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-Connecting-to-LPDDR2/m-p/545349#M85756</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-08-31T07:18:42Z</dc:date>
    </item>
  </channel>
</rss>

