IMX6 Quad MIPI CSI 2 Multiple Device Interfacing

tengri — Fri, 19 Aug 2016 09:23:05 GMT

Hi All,

For a video processing application we are intending to use an HDMI and a CVBS analog camera inputs with IMX6 Quad processor. ADV7481 is an ideal solution to achieve both requirements through MIPI CSI 2 bus, however in ADV7481 HDMI and CVBS inputs are connected to two separated MIPI transmitters (4 lane for HDMI and a single lane for CVBS) and driven by two separated differential clock signals.

My question is, can we interface these two separated transmitter signals to single MIPI CSI 2 input of the IMX6 processor ? Let's say we configure the HDMI output to be 1 lane MIPI (out of 4), so we have clkp/clkn, d0p/d0n for HDMI and by default clkp/clkn, d0p/d0n for CVBS output. Can these two differential clk lines be tied together ?

Thank You

Re: IMX6 Quad MIPI CSI 2 Multiple Device Interfacing

igorpadykov — Fri, 19 Aug 2016 23:57:42 GMT

Hi Anuradha

I am not sure if this will work, at least seems it was not tested.

However feasible option would be multiplex these streams in an FPGA.

Each stream in this case should use a different stream identifier (stream 0-3).

Best regards

igor

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topic IMX6 Quad MIPI CSI 2 Multiple Device Interfacing in i.MX Processors

IMX6 Quad MIPI CSI 2 Multiple Device Interfacing

Re: IMX6 Quad MIPI CSI 2 Multiple Device Interfacing