Config issue of LPDDR2

david5icp — Fri, 22 Jul 2016 11:58:31 GMT

Hello,

We have a customer board use 32 bit LPDDR2 and use 2 chip select. We can get config by DDR calibration tool and run "DDR Stess test" more than 2 hours. Verey things seems ok.

It's fail to use the table on my android project. But if I ignor "CS1" setting as below, the board can boot up to android.

How to config 32 bit lpddr2 and use 2 chip select ? Thanks!

// Channel0 : Configure DDR device:

//CS0

setmem /32 0x021b001c = 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0

setmem /32 0x021b001c = 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff

setmem /32 0x021b001c = 0x82018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=c2

setmem /32 0x021b001c = 0x06028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4

setmem /32 0x021b001c = 0x01038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6

//CS1

//setmem /32 0x021b001c = 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0

//setmem /32 0x021b001c = 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff

//setmem /32 0x021b001c = 0x82018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=c2

//setmem /32 0x021b001c = 0x06028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4

//setmem /32 0x021b001c = 0x01038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=2.drive=240/6

BR.

David Wu

Re: Config issue of LPDDR2

david5icp — Sat, 23 Jul 2016 14:17:46 GMT

Hello ~

It's working now. The problem caused by dcd_hdr and write_dcd_cmd. Please refer below:

dcd_hdr: .word 0x404802D2 /* Tag=0xD2, Len=72*8 + 4 + 4 = 0x0248, Ver=0x40 */

write_dcd_cmd: .word 0x044402CC /* Tag=0xCC, Len=72*8 + 4 = 0x0244, Param=0x04 */

BR.

David Wu

topic Config issue of LPDDR2 in i.MX Processors

Config issue of LPDDR2

Re: Config issue of LPDDR2