topic Re: MX6Q+LPDDR2(32bit) boot issue in i.MX Processors

MX6Q+LPDDR2(32bit) boot issue

david5icp — Wed, 15 Jun 2016 02:28:01 GMT

Hi Community,

We are also trying on MX6Q+LPDDR2 combined design. but make no sense why boot failure in mfg bootimage.

I had study similar issues from community: MX6Q+LPDDR2(32bit) boot issue

And i did same modifications on my board, but still no message come out form Debug Port (UART1). And can't finish MFG download.

Could you please help me to check this issue, Thanks!

**Notes for attached files:

Mx6DQSDL_LPDDR2_V006.inc ==> created by Mx6DQSDL LPDDR2 Script Aid V0.05.xlsx

Mx6DQSDL_LPDDR2_V006-400-Pass.log ==> DDR_Stress_Tester test log

flash_header.S ==> start from line 275 for our board. (it's works for other ddr3 platform if we change paramaters for ddr3)

Original Attachment has been moved to: MfgTool.log.zip

Original Attachment has been moved to: mx6q_sabresd.h.zip

Original Attachment has been moved to: flash_header.S.zip

Original Attachment has been moved to: Mx6DQSDL_LPDDR2_V006-400-Pass.log.zip

Original Attachment has been moved to: Mx6DQSDL_LPDDR2_V006.inc.zip

Re: MX6Q+LPDDR2(32bit) boot issue

Yuri — Fri, 17 Jun 2016 07:59:29 GMT

Hello,

Can You check, using a JTAG debugger if 400 MHz was set as CPU frequency ?

Also, have You implemented recommendations regarding "gate/ungate 528 pfd2",

from the mentioned thread ?

In particular, please look at

how to change DDR clock of i.mx6

Have a great day,
Yuri

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Re: MX6Q+LPDDR2(32bit) boot issue

david5icp — Wed, 22 Jun 2016 23:58:36 GMT

Hi Yuri,

The problem seems seems caused by LP2DDR power. It droped to 1.18V and can't pass DDR Stess test (ddr_stress_tester_v2.52). Now it works after adjust LPDDR2 power and pass DDR Stess test over 2 hours.

But it's still fail in the kernel, does it cause by ddr ? or have others issue ? Could you please give me some suggestion ?

Thanks!

Re: MX6Q+LPDDR2(32bit) boot issue

Yuri — Thu, 21 Jul 2016 09:16:15 GMT

Hello,

Again, is CPU frequency in Linux lower or equal than 400 MHz ?

Regards,

Yuri.

Re: MX6Q+LPDDR2(32bit) boot issue

david5icp — Thu, 21 Jul 2016 09:53:36 GMT

Hi Yuri,

Yes, the current setting is 396Mhz.

I have another problem also about lpddr2. As i say, i can pass ddr test more than 2 hours. I using the table to my android project. And I need to bypass cs1 setting of ch0. My can't boot If i set mode register on cs1.

And i just only have 512mb, because i only set cs0. The board will crash anywhere If bypass cs1 setting but use 1gb mode.

Does i.mx6q cat support single channel mode (32 bit mode) and use both cs0 and cs1 ? On android ? Thanks!

BR.

David Wu

Re: MX6Q+LPDDR2(32bit) boot issue

Yuri — Mon, 25 Jul 2016 08:39:01 GMT

Hello,

What is LPDDR2 part number ?

Is it possible to look at connection scheme between i.MX6 and LPDDR2 ?

Have a great day,

Yuri

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Re: MX6Q+LPDDR2(32bit) boot issue

david5icp — Mon, 25 Jul 2016 09:08:54 GMT

Hi Yuri,

The part number is MT29PZZZ8D5BKFTF. It's a EMCP. The HW seems ok. And the problem caused by dcd_hdr and write_dcd_cmd. Please refer below:

dcd_hdr: .word 0x404802D2 /* Tag=0xD2, Len=72*8 + 4 + 4 = 0x0248, Ver=0x40 */

write_dcd_cmd: .word 0x044402CC /* Tag=0xCC, Len=72*8 + 4 = 0x0244, Param=0x04 */

But We still have 20% fail rate on 1GB. These boards are normally on 512MB on Android. But fail to boot if change to 1GB mode (use 2 chip select). And these boards pass ddr test more than 2 hours. Do I missing somethings ?

And do I need to modify "MMDC0_ARB_BASE_ADDR" ?

#define MMDC0_ARB_BASE_ADDR 0x10000000

#define MMDC0_ARB_END_ADDR 0x7FFFFFFF

#define MMDC1_ARB_BASE_ADDR 0x80000000

#define MMDC1_ARB_END_ADDR 0xFFFFFFFF

Thanks!

David Wu

Re: MX6Q+LPDDR2(32bit) boot issue

Yuri — Thu, 28 Jul 2016 04:34:32 GMT

Hello,

For single channel LPDDR2 :

DDR Memory Map default config in BOOT_CFG3 should be 00 (Single DDR channel).

MMDCx_MDASP[CS0_END] should be set to DDR_CS_SIZE/32MB + 0x7
(DDR base address begins at 0x10000000, so MMDC0_ARB_BASE_ADDR is 0x10000000.

MMDC1 is not used and should not be initialized.
Use DRAM_RAS_B signals as LPDDR2_CS_B1_P0 (CS1 of the LPDDR2) and
DRAM_BA0 as LPDDR2_CS_B0_P0 (CS0 of the LPDDR2)

For MT29PZZZ8D5BKFTF : MMDCx_MDASP[CS0_END] = 0x17

Problems with instability may be solved with additional caps.

Please look at the recommendations, linked below.

https://community.nxp.com/servlet/JiveServlet/download/460403-1-284405/i.MX6%20Capacitor%20Placement%20Guidelines_Rev1.p…

Regards,

Yuri.