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    <title>topic Re: i.MX6SoloX uSDHC ADMA2 problem in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SoloX-uSDHC-ADMA2-problem/m-p/510362#M83109</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;&amp;nbsp; Please try using (system) DRAM memory, which supports bursts from the uSDHC. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 09 Mar 2016 08:48:54 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2016-03-09T08:48:54Z</dc:date>
    <item>
      <title>i.MX6SoloX uSDHC ADMA2 problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SoloX-uSDHC-ADMA2-problem/m-p/510361#M83108</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I'm porting the MQX 4.2 ESDHC driver on the i.MX6Solox and I'm having problems with the ADMA2.&lt;/P&gt;&lt;P&gt;The SDHC card is inserted and correctly initialized.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;When a try to read a block of 512 bytes, I initialize the ADMA descriptor with the following:&lt;/P&gt;&lt;P&gt;Low 32-bits: 0x0200 0023 (transfer 512 bytes, transfer data, End bit and Valid bit set)&lt;/P&gt;&lt;P&gt;High 32-bits: 0x1FFF AA08 (destination address in system memory (TCML))&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I get an ADMA2 error:&lt;/P&gt;&lt;P&gt;ADMA error status register = 0x00000009, according to the Reference Manual, it means the valid bit in the ADMA descriptor is cleared (which is not!).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The DMA is enabled (DMAEN bit set in register MIX_CTRL).&lt;/P&gt;&lt;P&gt;ADMA2 operation is selected (DMASEL=0x2 in register PROT_CTRL).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does anyone can help me to solve this problem?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;David&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 07 Mar 2016 09:58:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SoloX-uSDHC-ADMA2-problem/m-p/510361#M83108</guid>
      <dc:creator>davidjaouen</dc:creator>
      <dc:date>2016-03-07T09:58:27Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6SoloX uSDHC ADMA2 problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SoloX-uSDHC-ADMA2-problem/m-p/510362#M83109</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;&amp;nbsp; Please try using (system) DRAM memory, which supports bursts from the uSDHC. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 09 Mar 2016 08:48:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SoloX-uSDHC-ADMA2-problem/m-p/510362#M83109</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-03-09T08:48:54Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6SoloX uSDHC ADMA2 problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SoloX-uSDHC-ADMA2-problem/m-p/510363#M83110</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I tried using DRAM and it worked.&lt;/P&gt;&lt;P&gt;Thanks a lot.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;/P&gt;&lt;P&gt;David&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 09 Mar 2016 09:19:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SoloX-uSDHC-ADMA2-problem/m-p/510363#M83110</guid>
      <dc:creator>davidjaouen</dc:creator>
      <dc:date>2016-03-09T09:19:36Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6SoloX uSDHC ADMA2 problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SoloX-uSDHC-ADMA2-problem/m-p/1219055#M168179</link>
      <description>&lt;P&gt;Did you get the driver to work for the uSDHC? I'm also using MQX 4.2 (modified to run on the iMX6Q) and having issues reading using ADMA2. Everything appears to work - registers are what I would expect - but I get garbage in my read buffer. This is reading 1 block.&lt;/P&gt;</description>
      <pubDate>Thu, 21 Jan 2021 18:51:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SoloX-uSDHC-ADMA2-problem/m-p/1219055#M168179</guid>
      <dc:creator>ogj</dc:creator>
      <dc:date>2021-01-21T18:51:25Z</dc:date>
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