topic DDR3 Routing on IMX6 in i.MX Processors

DDR3 Routing on IMX6

bomsweigh — Mon, 15 Feb 2016 16:42:19 GMT

Hello,

One final question about the IMX6 layout.

In the hardware design checklist provided by NXP item 7 under DDR states that T is suggested four 4 or less DDR ICS

We have an IMX53 design using Flyby that worked great for us. We were hoping to reuse that part of the design.

Is there a problem with the IMX6 that makes T routing preferable to Fly-By?

Thanks,

7	Suggest to use "T" topology when the number of DDR chips are not more than four(two on top, two on bottom). Otherwise "Fly-by" Topology is recommended for more than two chips on same PCB side. Using the same as last SOM.

igorpadykov — Tue, 16 Feb 2016 01:38:06 GMT

Hi BOMs

hardware design checklist provided topologies carefully tested and verified

on real board designs. In general one can try other options, however it is

recommended to perform ibis modeling for each case.

Best regards

igor

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