<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックNVCC_DRAM Operating Ranges when DDR3L</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/NVCC-DRAM-Operating-Ranges-when-DDR3L/m-p/508285#M82771</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm using a i.MX6SL.&lt;/P&gt;&lt;P&gt;Let me confirm about DDR3L operating ranges.&lt;/P&gt;&lt;P&gt;What is DDR3L's I/O supply operating ranges ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There is no description about in Table 9 of datasheet.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Ko-hey&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 15 Feb 2016 08:07:42 GMT</pubDate>
    <dc:creator>ko-hey</dc:creator>
    <dc:date>2016-02-15T08:07:42Z</dc:date>
    <item>
      <title>NVCC_DRAM Operating Ranges when DDR3L</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NVCC-DRAM-Operating-Ranges-when-DDR3L/m-p/508285#M82771</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm using a i.MX6SL.&lt;/P&gt;&lt;P&gt;Let me confirm about DDR3L operating ranges.&lt;/P&gt;&lt;P&gt;What is DDR3L's I/O supply operating ranges ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There is no description about in Table 9 of datasheet.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Ko-hey&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 15 Feb 2016 08:07:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NVCC-DRAM-Operating-Ranges-when-DDR3L/m-p/508285#M82771</guid>
      <dc:creator>ko-hey</dc:creator>
      <dc:date>2016-02-15T08:07:42Z</dc:date>
    </item>
    <item>
      <title>Re: NVCC_DRAM Operating Ranges when DDR3L</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NVCC-DRAM-Operating-Ranges-when-DDR3L/m-p/508286#M82772</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;DDR3L memories are rated for the operation at 1.35V I/O voltage. Typical I/O voltage range for this type of memory is 1.29V to 1.45V with nominal value of 1.35V. i.MX6SL supports this I/O voltage range.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 16 Feb 2016 08:08:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NVCC-DRAM-Operating-Ranges-when-DDR3L/m-p/508286#M82772</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-02-16T08:08:03Z</dc:date>
    </item>
    <item>
      <title>Re: NVCC_DRAM Operating Ranges when DDR3L</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NVCC-DRAM-Operating-Ranges-when-DDR3L/m-p/508287#M82773</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Let me confirm again.&lt;/P&gt;&lt;P&gt;According to the IMX6SLCEC, NVCC_DRAM support 1.14 V to 1.574 V and DDR3L memory's operating range is &lt;SPAN style="color: #51626f; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; font-size: 14px;"&gt;1.29 V to 1.45 V&lt;/SPAN&gt;.&lt;/P&gt;&lt;P&gt;So there is no concern about using DDR3L.&lt;/P&gt;&lt;P&gt;Is it correct ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_0.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/53692i6DB97E0A000403BD/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_0.png" alt="pastedImage_0.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Ko-hey&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 16 Feb 2016 08:36:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NVCC-DRAM-Operating-Ranges-when-DDR3L/m-p/508287#M82773</guid>
      <dc:creator>ko-hey</dc:creator>
      <dc:date>2016-02-16T08:36:30Z</dc:date>
    </item>
    <item>
      <title>Re: NVCC_DRAM Operating Ranges when DDR3L</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NVCC-DRAM-Operating-Ranges-when-DDR3L/m-p/508288#M82774</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, this is correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 16 Feb 2016 11:58:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NVCC-DRAM-Operating-Ranges-when-DDR3L/m-p/508288#M82774</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-02-16T11:58:26Z</dc:date>
    </item>
    <item>
      <title>Re: NVCC_DRAM Operating Ranges when DDR3L</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NVCC-DRAM-Operating-Ranges-when-DDR3L/m-p/508289#M82775</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; COLOR: black; mso-bidi-font-size: 11.0pt; mso-ascii-font-family: Arial; mso-fareast-font-family:  MS Gothic ; mso-hansi-font-family: Arial;"&gt;Hi &lt;SPAN&gt;Artur&lt;/SPAN&gt;,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; COLOR: black; mso-bidi-font-size: 11.0pt; mso-ascii-font-family: Arial; mso-fareast-font-family:  MS Gothic ; mso-hansi-font-family: Arial;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; COLOR: black; mso-bidi-font-size: 11.0pt; mso-ascii-font-family: Arial; mso-fareast-font-family:  MS Gothic ; mso-hansi-font-family: Arial;"&gt;Thanks !&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; COLOR: black; mso-bidi-font-size: 11.0pt; mso-ascii-font-family: Arial; mso-fareast-font-family:  MS Gothic ; mso-hansi-font-family: Arial;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; COLOR: black; mso-bidi-font-size: 11.0pt; mso-ascii-font-family: Arial; mso-fareast-font-family:  MS Gothic ; mso-hansi-font-family: Arial;"&gt;Ko&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; COLOR: black; mso-bidi-font-size: 11.0pt; mso-ascii-font-family: Arial; mso-fareast-font-family:  MS Gothic ; mso-hansi-font-family: Arial;"&gt;-hey&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; COLOR: black; mso-bidi-font-size: 11.0pt; mso-ascii-font-family: Arial; mso-fareast-font-family:  MS Gothic ; mso-hansi-font-family: Arial;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 16 Feb 2016 12:05:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NVCC-DRAM-Operating-Ranges-when-DDR3L/m-p/508289#M82775</guid>
      <dc:creator>ko-hey</dc:creator>
      <dc:date>2016-02-16T12:05:46Z</dc:date>
    </item>
  </channel>
</rss>

