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    <title>i.MX Processors中的主题 IMX6DQ6SDLHDG pdf</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6DQ6SDLHDG-pdf/m-p/507702#M82664</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Regarding section 3.5.6 Four chips T topology routing examples: the pdf shows three layers of DDR3 routing, but there is clearly a fourth layer used that isn't shown. Would it be possible to get a screenshot of the missing layer?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 12 Feb 2016 20:10:34 GMT</pubDate>
    <dc:creator>jburk</dc:creator>
    <dc:date>2016-02-12T20:10:34Z</dc:date>
    <item>
      <title>IMX6DQ6SDLHDG pdf</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6DQ6SDLHDG-pdf/m-p/507702#M82664</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Regarding section 3.5.6 Four chips T topology routing examples: the pdf shows three layers of DDR3 routing, but there is clearly a fourth layer used that isn't shown. Would it be possible to get a screenshot of the missing layer?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 12 Feb 2016 20:10:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6DQ6SDLHDG-pdf/m-p/507702#M82664</guid>
      <dc:creator>jburk</dc:creator>
      <dc:date>2016-02-12T20:10:34Z</dc:date>
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    <item>
      <title>Re: IMX6DQ6SDLHDG pdf</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6DQ6SDLHDG-pdf/m-p/507703#M82665</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Generally, for all routing examples, refer to the i.MX6Q SABRE SD board PCB&lt;/P&gt;&lt;P&gt;design files, available as the i.MX6_SABRE_SDP_DESIGNFILES package on the NXP&lt;/P&gt;&lt;P&gt;web site (check the "Schematics" section):&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-processors-based-on-arm-cores/i.mx-6-processors/i.mx6qp/sabre-platform-for-smart-devices-reference-design-based-on-the-i.mx-6-series:RDIMX6SABREPLAT?fpsp=1&amp;amp;tab=Design_Tools_Tab" rel="nofollow"&gt;http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-processors-based-on-arm-cores/i.mx-6-processors/i.mx6qp/sabre-platform-for-smart-devices-reference-design-based-on-the-i.mx-6-series:RDIMX6SABREPLAT?fpsp=1&amp;amp;tab=Design_Tools_Tab&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 16 Feb 2016 07:20:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6DQ6SDLHDG-pdf/m-p/507703#M82665</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-02-16T07:20:27Z</dc:date>
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