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    <title>i.MX Processors中的主题 Re: Question, i.MX6SoloLite boot image parameters</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503726#M81673</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes - HAB version, please refer to Appendix D (HAB Version/Chip matrix) &lt;/P&gt;&lt;P&gt;of the recent AN4581,&amp;nbsp; Rev. 1, 10/2015.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.nxp.com/files/32bit/doc/app_note/AN4581.pd" title="http://cache.nxp.com/files/32bit/doc/app_note/AN4581.pd"&gt;http://cache.nxp.com/files/32bit/doc/app_note/AN4581.pd&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 28 Mar 2016 08:45:11 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2016-03-28T08:45:11Z</dc:date>
    <item>
      <title>Question, i.MX6SoloLite boot image parameters</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503723#M81670</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would like to ask about the meaning of parameters used in IVT and Boot Data structure of i.MX6SL boot image.&lt;/P&gt;&lt;P&gt;(Q1)&lt;/P&gt;&lt;P&gt;My customer is developing their board with i.MX6SoloLite. For i.MX6SL, my customer believes that the value of ‘header’ should be 0xD100 2040h.&lt;/P&gt;&lt;P&gt;Is it true?&lt;/P&gt;&lt;P&gt;(Q2)&lt;/P&gt;&lt;P&gt;As for the value of ‘entry', which of the address on OCRAM or on Boot-Device does the value specify?&lt;/P&gt;&lt;P&gt;(Q3)&lt;/P&gt;&lt;P&gt;As for ‘start’ in Boot Data structure, &lt;/P&gt;&lt;P&gt;Does the value specify the address in Boot Device relative to its Boot device base?&lt;/P&gt;&lt;P&gt;If so, the ‘start’ contains the value of zero always.&lt;/P&gt;&lt;P&gt;Correct?&lt;/P&gt;&lt;P&gt;(Q4)&lt;/P&gt;&lt;P&gt;According to the Figure-4 ‘Typical memory layout of an Unsigned Image’ in AN4581 Rev.0, the ‘lenth’ seems to be the length from the top to the end of Image Data.&lt;/P&gt;&lt;P&gt;Not only the length of Image Data.&lt;/P&gt;&lt;P&gt;Is it true?&lt;/P&gt;&lt;P&gt;(Q5)&lt;/P&gt;&lt;P&gt;In my customer’s use-case, they will not use secure-boot.&lt;/P&gt;&lt;P&gt;They thinks all of ‘self’, ‘plugin flag’ and ‘csf’ can be value of zero.&lt;/P&gt;&lt;P&gt;Correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 25 Mar 2016 06:51:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503723#M81670</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2016-03-25T06:51:38Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SoloLite boot image parameters</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503724#M81671</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class="tm6"&gt;&lt;SPAN class="tm7"&gt;&amp;nbsp; Please look at my comments below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;1.&lt;BR /&gt;&amp;nbsp; Please refer to Table 8-22 (IVT Header Format) of the i.MX6 SL RM.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;The IVT header includes three field : Tag, Length, Version.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;The field version may depend on boot ROM version : so,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;0xD100_2040 or 0xD100_2041 &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;&amp;nbsp; Also, please refer to Table 8-25 (DCD Header) of the i.MX6 SL RM.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;The DCD header includes three fields : Tag, Length, Version.&lt;BR /&gt;The field Length depends on length of the DCD ;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;version may depend on boot ROM version.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;2.&lt;BR /&gt;&amp;nbsp; The field “entry” is absolute address of the first instruction in memory &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;(OCRAM or DRAM).&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;3.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;&amp;nbsp; The field “start” of the Boot Data Structure is address in the memory, &lt;BR /&gt;where boot code is loaded. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;4.&lt;BR /&gt;&amp;nbsp; Correct, “length” is total image length.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;5.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="a______"&gt;&lt;SPAN class="tm7"&gt;&amp;nbsp; Yes, ‘self’, ‘plugin flag’ and ‘csf’ can be value of zero. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="tm9"&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 25 Mar 2016 07:33:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503724#M81671</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-03-25T07:33:43Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SoloLite boot image parameters</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503725#M81672</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your answer.&lt;/P&gt;&lt;P&gt;1.&lt;/P&gt;&lt;P&gt;Can i understand that the 'version' included in the header is 'HAB version'?&lt;/P&gt;&lt;P&gt;Where can I find the 'HAB version' of the chip?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Mar 2016 05:10:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503725#M81672</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2016-03-28T05:10:02Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SoloLite boot image parameters</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503726#M81673</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes - HAB version, please refer to Appendix D (HAB Version/Chip matrix) &lt;/P&gt;&lt;P&gt;of the recent AN4581,&amp;nbsp; Rev. 1, 10/2015.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.nxp.com/files/32bit/doc/app_note/AN4581.pd" title="http://cache.nxp.com/files/32bit/doc/app_note/AN4581.pd"&gt;http://cache.nxp.com/files/32bit/doc/app_note/AN4581.pd&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Mar 2016 08:45:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503726#M81673</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-03-28T08:45:11Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SoloLite boot image parameters</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503727#M81674</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The appendix-d only shows the HAB Ver. for Rev. 1.0 chip, MCIMX6LxxxxxxxA, of i.MX6SL.&lt;/P&gt;&lt;P&gt;How about Rev.1.2 chip of i.MX6SL?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Mar 2016 14:53:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503727#M81674</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2016-03-28T14:53:52Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SoloLite boot image parameters</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503728#M81675</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;HAB 4.1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Mar 2016 06:41:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-boot-image-parameters/m-p/503728#M81675</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-03-29T06:41:02Z</dc:date>
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