i.MX Processors中的主题 Boundary scan test issue on IMX6

Boundary scan test issue on IMX6

luc410 — Thu, 26 May 2016 06:54:41 GMT

On a design with IMX6 solo MCIMX6S7CVM08AC, connect to a Goepel tool, we have the following issue:

- TMS=1, 5 clocks -> state machine is in TLR state (OK).

- go to shift DR, put on TDI 52H (01010010), after 32+8 clocks we read on TDO:

0101010 00011000100100011011000000011101 (first bit right) where

-first "1" IEE1149.1 requirement

-"00000001110" & -- Manufacturer Identity

-"1000100100011011" & -- Part Number

-"0010" & -- Version

-"01010010" (52H) Goepel "Testbyte" : this testbyte is shifted through test bus chain to verified test bus.

---> This test is OK

- go to IR, load bypass instruction.

- return to DR shift, put Testbyte on TDI, read on TDO:

- 010100100 (first bit right):

- first "0" : bypass register

- 01010010: Test byte

---> This test is OK

- go to IR, load sample/preload instruction.

- return to DR shift, put on TDI Testbyte (01010010) then 010101...(652 bit, it's the boundary scan lenght).

- after 652 + 8 clock we must read Testbyte --> This test fail, all bit are set at 0.

In fact, we cannot control the BSR (Boundary Scan Register), we try also with Extest instruction, it's the same answer.

Fuse are not burned on the board.

We try the same test on a SABRE PLATEFORM, with a PCIMX6U8DVM10AB, the same test is OK.

Compliance pattern are the same in the two case : "(TEST_MODE, JTAG_MOD, POR_B)= (011)".

Could you help us, please.

Regards.

Luc Dalongeville

Re: Boundary scan test issue on IMX6

Yuri — Thu, 26 May 2016 07:01:25 GMT

Hello,

If boundary scan test is used, PCIE_VP, PCIE_VPH, and PCIE_VPTX must remain powered.

Please check it.

Have a great day,

Yuri

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Re: Boundary scan test issue on IMX6

luc410 — Thu, 26 May 2016 08:46:26 GMT

Hello Yuri,

Information in HW manual is ambiguous:

"SATA and PCIe are not digital interfaces, but these modules provide built-in support for the IEEE 1149.6 extension for AC testing of their pins. Therefore, these modules must also be powered when utilizing a scan chain that contains the pins from these modules, or the scan chain does not function properly."

We use IEEE 1149.1 , so we skip this comment.

I think this mandatory information could be available in bsdl file, under "Design-warning" attribute,
to help test engineering team.
About the issue, we check the design and PCIE interface is not powered...

Have a nice day

Luc