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    <title>topic Re: How to check whether the data transfer was completed, with FEC of i.MX25. in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/How-to-check-whether-the-data-transfer-was-completed-with-FEC-of/m-p/500799#M80990</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; You wrote "&lt;SPAN style="color: #51626f; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif;"&gt; that ethernet packet was not sent although TxBD[R] was cleared&lt;/SPAN&gt;". &lt;/P&gt;&lt;P&gt;This may take place, when the TxBD was processed, but data was not sent yet&lt;/P&gt;&lt;P&gt;because of internal FIFO.&amp;nbsp; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 06 Jan 2016 04:21:30 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2016-01-06T04:21:30Z</dc:date>
    <item>
      <title>How to check whether the data transfer was completed, with FEC of i.MX25.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-check-whether-the-data-transfer-was-completed-with-FEC-of/m-p/500796#M80987</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In FEC of i.MX25, would you tell me about a method to check that data transfer was completed?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We refer to the following point of the reference manual.&lt;/P&gt;&lt;P&gt;25.5.2.1 Driver/DMA Operation with Buffer Descriptors (P.850)&lt;BR /&gt;-----&lt;BR /&gt;"After the data DMA is complete and the buffer descriptor status bits have been &lt;/P&gt;&lt;P&gt;written by the DMA engine, the RxBD[E] or TxBD[R] bit is cleared by hardware to &lt;/P&gt;&lt;P&gt;signal the buffer has been “consumed.” Software can poll the BDs to detect &lt;/P&gt;&lt;P&gt;when the buffers have been consumed or can rely on the buffer/frame interrupts."&lt;BR /&gt;-----&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;According to this, we understand there is two methods to check the data transfer of FEC was completed.&lt;/P&gt;&lt;P&gt;A) SW polls it until TxBD[R] is cleared.&lt;BR /&gt;B) SW relies on the buffer/frame(EIR[TXF]) interrupts.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The frame may be constructed in a number of Buffers.&lt;BR /&gt;However, in the Linux BSP_FEC driver of NXP, one frame is constructed by one buffer.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;===================================&lt;BR /&gt;　static status_t xio_write( XCONTAINER* x_contnr, void*buffer, size_t length )&lt;BR /&gt;　→&lt;BR /&gt;　status_t WriteFrame( CTB_LAN* control, void* buffer, size_tlength )&lt;BR /&gt;　→&lt;BR /&gt;　static status_t SendBuf( CTB_LAN* control, void* data, size_tsize )&lt;BR /&gt;===================================&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We used a method of (A).&lt;BR /&gt;However, we were not able to detect transfer completion correctly.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;When a method of (B) is used, it seems that we are able to detect transfer completion correctly.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We do not understand difference between (A) and (B).&lt;BR /&gt;We want to know the reason that we cannot detect correctly by (A).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;May I have advice?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Yuuki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 22 Dec 2015 07:10:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-check-whether-the-data-transfer-was-completed-with-FEC-of/m-p/500796#M80987</guid>
      <dc:creator>yuuki</dc:creator>
      <dc:date>2015-12-22T07:10:31Z</dc:date>
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    <item>
      <title>Re: How to check whether the data transfer was completed, with FEC of i.MX25.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-check-whether-the-data-transfer-was-completed-with-FEC-of/m-p/500797#M80988</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt; The event EIR[TXF] means the whole frame (which may contain several TxBDs &lt;BR /&gt; and buffers) is sent. The event TxBD[R] cleared (after being set) means, that &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;only single buffer has been sent. Generally EIR[TXB] should be also set in such case. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Note, FEC Buffer Descriptors (BD) are described as following :&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;typedef struct BufferDescriptor&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;{&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; U16 length;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; // transfer length&amp;nbsp; - this field is Low Significant 16-bit field of 32-bit word&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; U16 cstatus;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; // control and status - Most Significant 16-bit field &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; U32 addr;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; // buffer address&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;}BD;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Please pay attention, the first structure field is length, not status as it is &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;described in the Reference Manual. This is because of little endian mode of the &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;ARM core.&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt; There are requirements for FEC BD ring and buffers to be properly aligned :&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;BD ring should 128-bit aligned, receive data buffers 16-bytes aligned, transmit &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;buffers - 32-bit aligned.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Dec 2015 07:30:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-check-whether-the-data-transfer-was-completed-with-FEC-of/m-p/500797#M80988</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-12-23T07:30:33Z</dc:date>
    </item>
    <item>
      <title>Re: How to check whether the data transfer was completed, with FEC of i.MX25.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-check-whether-the-data-transfer-was-completed-with-FEC-of/m-p/500798#M80989</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you for your quick reply.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;We would like to ask an additional question.&lt;/P&gt;&lt;P&gt;Previously we confirmed it by polling if TxBD[R] was cleared because a frame had only one BD.&lt;BR /&gt;However we found an issue that ethernet packet was not sent although TxBD[R] was cleared.&lt;/P&gt;&lt;P&gt;So we modified the driver to confirm the sending completion by receiving interrupt with EIR[TXF].&lt;BR /&gt;After that, the issue does not occur.&lt;/P&gt;&lt;P&gt;Eventually should we confirm the sending completion by receiving interrupt with EIR[TXF] though our sending frame has only one BD ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Yuuki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 25 Dec 2015 00:05:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-check-whether-the-data-transfer-was-completed-with-FEC-of/m-p/500798#M80989</guid>
      <dc:creator>yuuki</dc:creator>
      <dc:date>2015-12-25T00:05:10Z</dc:date>
    </item>
    <item>
      <title>Re: How to check whether the data transfer was completed, with FEC of i.MX25.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-check-whether-the-data-transfer-was-completed-with-FEC-of/m-p/500799#M80990</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; You wrote "&lt;SPAN style="color: #51626f; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif;"&gt; that ethernet packet was not sent although TxBD[R] was cleared&lt;/SPAN&gt;". &lt;/P&gt;&lt;P&gt;This may take place, when the TxBD was processed, but data was not sent yet&lt;/P&gt;&lt;P&gt;because of internal FIFO.&amp;nbsp; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 06 Jan 2016 04:21:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-check-whether-the-data-transfer-was-completed-with-FEC-of/m-p/500799#M80990</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-01-06T04:21:30Z</dc:date>
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