topic Re: Relation between PLL Freq and SSI's sys clock in i.MX Processors

Relation between PLL Freq and SSI's sys clock

yehudastern — Wed, 10 Feb 2016 17:52:10 GMT

Hi,

1. The relation between PLL Freq and SSI's sys clock is given by SSIDIV (in CCM). Is that the product of SSIx_clk_pred and SSIx_clk_podf ?

(I set PLL4 frequency to 688.128 MHz and SSIDIV to 56, and would expect SSI's sys clock to be 12.288 MHz).

2. mxc_wm8962_init() function in board-mx6q_sabresd.c includes the following code:

rate = clk_round_rate(clko, 24000000);

clk_set_rate(clko, rate);

wm8962_data.sysclk = rate;

But when I read wm8962_data.sysclk, I receive 86.016 MHz, which is 7 times the expected value.

What's the purpose of this code? Can it simply be replaced with: rate = clk_set_rate(clko, 12288000); ?

3. When measuring the Serial BIT clock with a scope, I always get 1.4112 MHz instead of 1.536 MHz.

Any idea why? (is that the default value given by the driver?)

Thanks

Re: Relation between PLL Freq and SSI's sys clock

igorpadykov — Thu, 11 Feb 2016 01:06:11 GMT

Hi Yehuda

1. I believe you are right, in particular Figure 61-22. SSI Transmit Clock Generator Block Diagram

i.MX6DQ RM http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

shows origin of SSI's sys clock

2. please look at linux clock framework description on web resources, like

http://elinux.org/images/b/b8/Elc2013_Clement.pdf

3. seems one needs to reprogram pll, as function like clk_round_rate()

just chooses frequency close to necessary

Best regards

igor

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Re: Relation between PLL Freq and SSI's sys clock

yehudastern — Thu, 11 Feb 2016 13:01:16 GMT

Hi Igor,

1. Figure 61-22 (SSI Transmit Clock Generator Block Diagram in i.MX6DQ RM) shows SSI's sys clock as the input clock, but doesn't show its origin.

I need to verify whether SSIDIV in Table 61-7 is the product of SSIx_clk_pred and SSIx_clk_podf (taken from CCM_CS1CDR & CCM_CS1CDR registers).

2. Is there any way to read the real SSI's sys clock inside i.MX6 ?

3. Please correct me if I'm wrong:

- Since Serial BIT clock measured with a scope is an input to the codec, and since mxc_wm8962_init() function only deals with the codecs internal PLL, the

Serial BIT clock cannot be influenced by this function, and can only be influenced by the contents of the following registers (i.e. no other registers are involved):

CCM_ANALOG_PLL_AUDIO, (BTW, what's the difference between this register and CCM_ANALOG_PLL_AUDIO_SET / CLR ?)

CCM_ANALOG_PLL_AUDIO_NUM,

CCM_ANALOG_PLL_AUDIO_DENOM,

CCM_CS1CDR / CCM_CS2CDR

CCM_CSCMR1,

SSI1_STCCR / SSI2_STCCR / SSI2_STCCR.

Yehuda

Re: Relation between PLL Freq and SSI's sys clock

igorpadykov — Fri, 12 Feb 2016 01:32:47 GMT

Hi Yehuda

you can output some clocks for check using

CCM_CCOSR register

~igor

Re: Relation between PLL Freq and SSI's sys clock

yehudastern — Fri, 12 Feb 2016 15:14:10 GMT

Hi Igor,

Thanks. It seems that SSI's sys clock can also be output to the network clock as illustrated on figure 61-22.

I would appreciate it if you can also advise regarding questions 1 & 3.

Thanks.