i.MX Processors中的主题 Re: Issue About CS0_END

Issue About CS0_END

tony_l_cai — Tue, 19 Jan 2016 07:31:45 GMT

Hi all，

I get lot of info regarding to DDR2 2-channel settings in CS0_END, but I need the DDR3 1-channel settings in CS0_END, So how to set on MX6DL?

And on my board, DDR3 1GB, the scripts show CS0_END=0x27 but as following:

the CS0_END should be 0x1f, so could you help me?

Re: Issue About CS0_END

Yuri — Tue, 19 Jan 2016 08:17:17 GMT

Hello,

MMDCx_MDASP[CS0_END] should be set to DDR_CS_SIZE/32MB + 0x7 (DDR base

address begins at 0x10000000).

That is, for 1GB CS0_END = 0x27

Have a great day,
Yuri

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Re: Issue About CS0_END

tony_l_cai — Tue, 19 Jan 2016 08:47:36 GMT

Hi Yuri,

From your description and the above, the size=(0x27+1)*256Mb /8=1280MB, but My total density is 1024MB, If the CS0_END=0x1F,I can understand, and It also can correspond to the chart. Why to enlarge?

And from your opinion, the base addr=0x1000 0000, the offset=1280MB, So the end addr=0x1014 0000?

Because I need to test DDR in uboot by uboot cmd "mtest",the start addr and end addr should be provided. I need to calc it, But actually, the physical memory is not so large, how to understand?

Thank you~

Re: Issue About CS0_END

Yuri — Tue, 19 Jan 2016 09:41:05 GMT

Start address = 0x1000_0000

End address = 0x5000_0000 - 1

Regards,

Yuri