MIPI DSI mipi clock

felixh — Wed, 23 Mar 2016 16:16:47 GMT

I'm using a Agilent DSO9084A Oscilloscope to analyze a two lane MIPI DSI bus.

The MIPI analyzation software don't use the external MIPI clk from the imx6 cpu, but instead needs the data rate specified.

I need to know the exact mipi clk used when configuring my display.

For example, when i configure my display to use a max_phy_clk=300, in mipi_lcd_config, what is the exact mipi clk generated from this.

I'm using kernel driver from branch imx_3.14.38_6qp_ga

Best Regards

Felix

Re: MIPI DSI mipi clock

b36401 — Mon, 18 Apr 2016 06:24:59 GMT

MIPI DSI interface of i.MX6S processor supports from 80 Mbps up to 1 Gbps speed per data lane.

DSI receiver cores can mange one clock lane and up to 4 data lanes through the lane management,

however two data lanes are implemented in the transmitter D-PHY, therefore the maximum throughput of display port is 2Gbps.

Please refer to 9.10.2 and 9.10.3 chapters of i.MX 6Solo/6DualLite Applications Processor Reference Manual for more details.

Have a great day,

Victor

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