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    <title>topic Re: Is the DAP which enable to read CPU registers during JTAG debug session ?  in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Is-the-DAP-which-enable-to-read-CPU-registers-during-JTAG-debug/m-p/499687#M80688</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Fabien&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q1] Does the OnCE portion is used for debugging only the SDMA 32-bit RISC processor ? :&lt;/P&gt;&lt;P&gt;Yes, OnCE is unrelated if you are trying to debug Cortex-A9 core.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q2] If I want to halt Cortex-A9 core, read its registers this is the DAP module which work on the JTAG chain ? :&lt;/P&gt;&lt;P&gt;Correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;To give you an idea, here is the jtag chain description for iMX6Q we use with&lt;/P&gt;&lt;P&gt;our debugger (BDI3000 from Abatron) :&lt;/P&gt;&lt;P&gt;#0 SCANPRED 2 9 ;count for SJC and SDMA&lt;/P&gt;&lt;P&gt;#0 SCANSUCC 0 0 ;no device after DAP&lt;/P&gt;&lt;P&gt;Which tells our debugger to skip the first 2 devices in&lt;/P&gt;&lt;P&gt;the scan chain with a IR length of 9. Your JTAG&lt;/P&gt;&lt;P&gt;debugger might have a different way to describe the&lt;/P&gt;&lt;P&gt;DAP in the chain.&lt;/P&gt;&lt;P&gt;Hope this helps&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Sinan Akman&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 13 Apr 2016 15:24:15 GMT</pubDate>
    <dc:creator>sinanakman</dc:creator>
    <dc:date>2016-04-13T15:24:15Z</dc:date>
    <item>
      <title>Is the DAP which enable to read CPU registers during JTAG debug session ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-the-DAP-which-enable-to-read-CPU-registers-during-JTAG-debug/m-p/499686#M80687</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I need some precision about JTAG scan chain.&lt;/P&gt;&lt;P&gt;I'm misunderstanding what is the device which halt/run the CPU during a JTAG debug session.&lt;/P&gt;&lt;P&gt;For example when I connect a JTAG debug tool to the JTAG pins, which device on the JTAG daisy-chain enable to read the CPU registers or halt it ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the document IMX6SDLRM, Rev. 2, 04/2014:&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.nxp.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf?fsrch=1&amp;amp;sr=1&amp;amp;pageNum=1" title="http://cache.nxp.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf?fsrch=1&amp;amp;sr=1&amp;amp;pageNum=1"&gt;http://cache.nxp.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf?fsrch=1&amp;amp;sr=1&amp;amp;pageNum=1&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It is explaned (p. 364/5829):&lt;/P&gt;&lt;P&gt;"The SJC module is the bridge between external development and test instrumentation and&lt;/P&gt;&lt;P&gt;the internal JTAG-accessible debug and test resources."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;An overview of the JTAG architecture&amp;nbsp; is given(p. 4914/5829)&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="SJC2.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/31936i0866BE2B0E2B98AE/image-size/large?v=v2&amp;amp;px=999" role="button" title="SJC2.jpg" alt="SJC2.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;On the JTAG daisy-chain there are in particular 2 devices :&lt;/P&gt;&lt;P&gt;- The OnCE (On chip Emulator) of the SDMA&lt;/P&gt;&lt;P&gt;- The DAP (Debug Acces Port)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It is explained (p.366/5829) :&lt;/P&gt;&lt;P&gt;"The SDMA debug features are primarily defined by the OnCE portion of its design."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please, I need some precision:&lt;/P&gt;&lt;P&gt;[Q1] Does the OnCE portion is used for debugging only the SDMA 32-bit RISC processor ?&lt;/P&gt;&lt;P&gt;[Q2] If I want to halt Cortex-A9 core, read its registers this is the DAP module which work on the JTAG chain ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for any help.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Fabien.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Apr 2016 10:18:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-the-DAP-which-enable-to-read-CPU-registers-during-JTAG-debug/m-p/499686#M80687</guid>
      <dc:creator>fmajeric</dc:creator>
      <dc:date>2016-04-13T10:18:53Z</dc:date>
    </item>
    <item>
      <title>Re: Is the DAP which enable to read CPU registers during JTAG debug session ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-the-DAP-which-enable-to-read-CPU-registers-during-JTAG-debug/m-p/499687#M80688</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Fabien&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q1] Does the OnCE portion is used for debugging only the SDMA 32-bit RISC processor ? :&lt;/P&gt;&lt;P&gt;Yes, OnCE is unrelated if you are trying to debug Cortex-A9 core.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q2] If I want to halt Cortex-A9 core, read its registers this is the DAP module which work on the JTAG chain ? :&lt;/P&gt;&lt;P&gt;Correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;To give you an idea, here is the jtag chain description for iMX6Q we use with&lt;/P&gt;&lt;P&gt;our debugger (BDI3000 from Abatron) :&lt;/P&gt;&lt;P&gt;#0 SCANPRED 2 9 ;count for SJC and SDMA&lt;/P&gt;&lt;P&gt;#0 SCANSUCC 0 0 ;no device after DAP&lt;/P&gt;&lt;P&gt;Which tells our debugger to skip the first 2 devices in&lt;/P&gt;&lt;P&gt;the scan chain with a IR length of 9. Your JTAG&lt;/P&gt;&lt;P&gt;debugger might have a different way to describe the&lt;/P&gt;&lt;P&gt;DAP in the chain.&lt;/P&gt;&lt;P&gt;Hope this helps&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Sinan Akman&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Apr 2016 15:24:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-the-DAP-which-enable-to-read-CPU-registers-during-JTAG-debug/m-p/499687#M80688</guid>
      <dc:creator>sinanakman</dc:creator>
      <dc:date>2016-04-13T15:24:15Z</dc:date>
    </item>
    <item>
      <title>Re: Is the DAP which enable to read CPU registers during JTAG debug session ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-the-DAP-which-enable-to-read-CPU-registers-during-JTAG-debug/m-p/499688#M80689</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The answer to both of your questions is "Yes".&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 19 Apr 2016 07:01:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-the-DAP-which-enable-to-read-CPU-registers-during-JTAG-debug/m-p/499688#M80689</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-04-19T07:01:25Z</dc:date>
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