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    <title>topic Re: DDR3L SDRAM interface with iMX6 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498778#M80442</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jive-link-email-small" href="mailto:Yuri.Muhin@nxp.com"&gt;Yuri.Muhin@nxp.com&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 30 Mar 2016 07:46:50 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2016-03-30T07:46:50Z</dc:date>
    <item>
      <title>DDR3L SDRAM interface with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498773#M80437</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, I am using DDR3L SDRAM with 32 bit interface with iMX6 in my design. iMX6 has 64bit data capacity. If i am using only 32 bit channel 0, so do i need to keep NC channel1 or is there any specific connections/level i need to do in my design. Thanks, Mrudang&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Mar 2016 04:42:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498773#M80437</guid>
      <dc:creator>mrudangshelat</dc:creator>
      <dc:date>2016-03-23T04:42:20Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L SDRAM interface with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498774#M80438</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; Unused signals / pins of 64-bit memory I/F (in 32-bit or 16-bit mode) may be left float, &lt;BR /&gt;as stated in section 5 (DRAM interface requirements for migration) of app note AN4397&lt;/P&gt;&lt;P&gt;(Common Hardware Design for i.MX&amp;nbsp; 6Dual/6Quad and i.MX 6Solo/6DualLite).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Mar 2016 04:50:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498774#M80438</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-03-23T04:50:23Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L SDRAM interface with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498775#M80439</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;Thanks for reply.&lt;/P&gt;&lt;P&gt;I have attached my design, can you please review it and provide me feedback.&lt;/P&gt;&lt;P&gt;I have added 2 files (16bit and 32bit design)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; regards,&lt;/P&gt;&lt;P&gt;Mrudang&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="DDR3L - iMX6 Interface - 16bit.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/3219i4798EF54742930F4/image-size/large?v=v2&amp;amp;px=999" role="button" title="DDR3L - iMX6 Interface - 16bit.jpg" alt="DDR3L - iMX6 Interface - 16bit.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="DDR3L - iMX6 Interface - 32bit.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/26574i3D7A6AA1A94DA703/image-size/large?v=v2&amp;amp;px=999" role="button" title="DDR3L - iMX6 Interface - 32bit.jpg" alt="DDR3L - iMX6 Interface - 32bit.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Mar 2016 05:31:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498775#M80439</guid>
      <dc:creator>mrudangshelat</dc:creator>
      <dc:date>2016-03-30T05:31:46Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L SDRAM interface with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498776#M80440</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; Quality of the figures is not good. Please create request and provide original scheme &lt;BR /&gt;sheets.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-329745"&gt;How to submit a new question for NXP Support&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Mar 2016 07:01:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498776#M80440</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-03-30T07:01:57Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L SDRAM interface with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498777#M80441</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for prompt support.&lt;/P&gt;&lt;P&gt;I have tried to open new request but due to some issue it's not accepting my User name and password.&lt;/P&gt;&lt;P&gt;Could you please provide me your email address or alternate contact details, so I can send you PDF file for review.&lt;/P&gt;&lt;P&gt;And I am also not able to attach PDF design file with this message.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;Thanks &amp;amp; regards,&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;Mrudang&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Mar 2016 07:23:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498777#M80441</guid>
      <dc:creator>mrudangshelat</dc:creator>
      <dc:date>2016-03-30T07:23:07Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L SDRAM interface with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498778#M80442</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jive-link-email-small" href="mailto:Yuri.Muhin@nxp.com"&gt;Yuri.Muhin@nxp.com&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Mar 2016 07:46:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498778#M80442</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-03-30T07:46:50Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L SDRAM interface with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498779#M80443</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Mar 2016 08:03:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498779#M80443</guid>
      <dc:creator>mrudangshelat</dc:creator>
      <dc:date>2016-03-30T08:03:58Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L SDRAM interface with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498780#M80444</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I send comments via e-mail.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Mar 2016 08:39:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498780#M80444</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2016-03-30T08:39:35Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L SDRAM interface with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498781#M80445</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For your valuable feedback.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Mar 2016 04:46:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-SDRAM-interface-with-iMX6/m-p/498781#M80445</guid>
      <dc:creator>mrudangshelat</dc:creator>
      <dc:date>2016-03-31T04:46:17Z</dc:date>
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