i.MX ProcessorsのトピックRe: AIPSTZ in imx6.

AIPSTZ in imx6.

myungjinhwang — Wed, 23 Mar 2016 09:29:40 GMT

Dear NXP team.

I have 2 questiosns...

1. AIPTZ

There are AIPSTZ_PACRs, AIPSTZ_OPACRs registers as bellow in the reference menual(Document Number: IMX6DQRM Rev. 3, 07/2015).

but no descriptions of AIPSTZ_PACRs, it only explain AIPSTZ_OPACRs

where can i find AIPSTZ_PACRs?

13.6 Initialization Information

The AIPS bridge should be programmed before use.

The following registers should be initialized: The Master Privilege Registers

(AIPSTZ_MPRs), the Peripheral Access Control registers (AIPSTZ_PACRs), and the

Off-platform Peripheral Access Control registers (AIPSTZ_OPACRs) described in AIPSTZ Memory Map/Register Definition.

2. AIPSTZx_MPR

As bellow description, I need to control AIPSTZx_MPR register.

and i could see something wonder.

I think i could write only AIPSTZx_MPR(0x0207_C000) to control MOROT0, MOROT1, MOROT2, MOROT3

But in the u-boot source code, it write 0x0207_C000 and 0x0207_C004 to control MOROT0, MOROT1 as bellow.

It's different with the reference menual.

then I should write 0x0207_C008,0x0207_C00C to control MOROT2, MOROT3?

Please give some guide in detailed as possible.

	/*
	* Set all MPROTx to be non-bufferable, trusted for R/W,
	* not forced to user-mode.
	*/
	writel(0x77777777, &aips1->mprot0);
	writel(0x77777777, &aips1->mprot1);

and the physical memory dump is that

________address|________0________4________8________C_0123456789ABCDEF

AZSD:0207C000|>77777777 77777777 ???????? ???????? wwwwwwww????????

AZSD:0207C010| ???????? ???????? ???????? ???????? ????????????????

Have a good day.

MyungJin Hwang

Re: AIPSTZ in imx6.

Yuri — Thu, 24 Mar 2016 09:46:12 GMT

Hello,

Below are definitions for registers offsets :

#define AIPS_MPROT0_7_OFFSET 0x00

#define AIPS_MPROT8_15_OFFSET 0x04

#define AIPS_PACR0_7_OFFSET 0x20

#define AIPS_PACR8_15_OFFSET 0x24

#define AIPS_PACR16_23_OFFSET 0x28

#define AIPS_PACR24_31_OFFSET 0x2C

#define AIPS_OPACR0_7_OFFSET 0x40

#define AIPS_OPACR8_15_OFFSET 0x44

#define AIPS_OPACR16_23_OFFSET 0x48

#define AIPS_OPACR24_31_OFFSET 0x4C

#define AIPS_OPACR32_33_OFFSET 0x50

The AIPS_PACR registers are skipped in the RM.

2.
U-boot is based on preliminary i.MX6 specs, where master’s bit fields 4-15 (MPROT4-15)

were not declared as Reserved. Please follow the recent RM.

Have a great day,
Yuri

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Re: AIPSTZ in imx6.

myungjinhwang — Thu, 24 Mar 2016 14:11:50 GMT

Hi Yuri.

Thank you very much for the detailed answer.

It's very helpful.

Have a great day.

MyungJin