topic Re: About SSI_CLK_ROOT specification. in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/About-SSI-CLK-ROOT-specification/m-p/497310#M80117 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P></P><P><SPAN style="font-family: 'Times New Roman'; font-size: 16,0000pt;">&nbsp;&nbsp; Sources of the SSI_CLK_ROOT (PLL4, PLL3) are shown on Figure 18-2 (Clock Tree - Part 1)</SPAN></P><P><SPAN style="font-family: 'Times New Roman'; font-size: 16,0000pt;">of the I.MX6 S/DL RM.&nbsp;&nbsp; Strictly speaking, jitter, accuracy, duty parameters of internal PLLs are </SPAN><SPAN style="font-size: 16,0000pt; font-family: 'Times New Roman';">not specified.&nbsp; <BR />The only specified parameters may be found in the Datasheet(s) in section “PLL’s </SPAN><SPAN style="font-family: 'Times New Roman'; font-size: 16,0000pt;">Electrical Characteristics”.&nbsp; <BR />Nevertheless, we can refer to 24 MHz crystal tolerance guidelines of </SPAN><SPAN style="font-family: 'Times New Roman'; font-size: 16,0000pt;"><SPAN style="font-family: 'Times New Roman'; font-size: 16,0000pt;">the Hardware Development Guide, assuming stability (thermal, voltage and other) of PLL output clock </SPAN><SPAN style="font-size: 16,0000pt; font-family: 'Times New Roman';">is fully defined <BR />by external crystal / oscillator in order to meet USB, PCIe, Ethernet clock specs. </SPAN></SPAN></P><P><BR />Have a great day,<BR />Yuri</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Wed, 10 Feb 2016 08:52:02 GMT Yuri 2016-02-10T08:52:02Z About SSI_CLK_ROOT specification. https://community.nxp.com/t5/i-MX-Processors/About-SSI-CLK-ROOT-specification/m-p/497309#M80116 <HTML><HEAD></HEAD><BODY><P>Hi community.</P><P></P><P>Our customer has below question.</P><P></P><P><SPAN class="hps">About duty specification of </SPAN><SPAN class="hps">SSI_CLK_ROOT</SPAN> <SPAN class="hps">of</SPAN> <SPAN class="hps">i.MX6DL.</SPAN></P><P></P><P><SPAN class="hps">Please tell us the</SPAN> <SPAN class="hps">specifications for</SPAN> <SPAN class="hps">Duty</SPAN> <SPAN class="hps">of</SPAN> <SPAN class="hps">SSI_CLK_ROOT.</SPAN></P><P><SPAN class="hps">If you have any</SPAN> <SPAN class="hps">Duty-SPEC,</SPAN> <SPAN class="hps">please</SPAN> <SPAN class="hps">tell me the</SPAN> <SPAN class="hps">Max / Typ/ Min.</SPAN></P></BODY></HTML> Tue, 09 Feb 2016 08:51:14 GMT https://community.nxp.com/t5/i-MX-Processors/About-SSI-CLK-ROOT-specification/m-p/497309#M80116 takashitakahash 2016-02-09T08:51:14Z Re: About SSI_CLK_ROOT specification. https://community.nxp.com/t5/i-MX-Processors/About-SSI-CLK-ROOT-specification/m-p/497310#M80117 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P></P><P><SPAN style="font-family: 'Times New Roman'; font-size: 16,0000pt;">&nbsp;&nbsp; Sources of the SSI_CLK_ROOT (PLL4, PLL3) are shown on Figure 18-2 (Clock Tree - Part 1)</SPAN></P><P><SPAN style="font-family: 'Times New Roman'; font-size: 16,0000pt;">of the I.MX6 S/DL RM.&nbsp;&nbsp; Strictly speaking, jitter, accuracy, duty parameters of internal PLLs are </SPAN><SPAN style="font-size: 16,0000pt; font-family: 'Times New Roman';">not specified.&nbsp; <BR />The only specified parameters may be found in the Datasheet(s) in section “PLL’s </SPAN><SPAN style="font-family: 'Times New Roman'; font-size: 16,0000pt;">Electrical Characteristics”.&nbsp; <BR />Nevertheless, we can refer to 24 MHz crystal tolerance guidelines of </SPAN><SPAN style="font-family: 'Times New Roman'; font-size: 16,0000pt;"><SPAN style="font-family: 'Times New Roman'; font-size: 16,0000pt;">the Hardware Development Guide, assuming stability (thermal, voltage and other) of PLL output clock </SPAN><SPAN style="font-size: 16,0000pt; font-family: 'Times New Roman';">is fully defined <BR />by external crystal / oscillator in order to meet USB, PCIe, Ethernet clock specs. </SPAN></SPAN></P><P><BR />Have a great day,<BR />Yuri</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Wed, 10 Feb 2016 08:52:02 GMT https://community.nxp.com/t5/i-MX-Processors/About-SSI-CLK-ROOT-specification/m-p/497310#M80117 Yuri 2016-02-10T08:52:02Z