Questions on IPU/DC configuration for 8 bit parallel display bus

dehuanxin — Tue, 03 May 2016 14:49:59 GMT

I'm trying to connect a IMX6Q SoC to a LCD display with 8 bit bus, using RGB888 format.

I'm looking at linux-fslc/ipu_disp.c at 3.14-1.1.x-imx · Freescale/linux-fslc · GitHub

My plan is to drive the DC sync wave 3 times faster and use three set of maps to map RGB24 to R8/G8/B8 in each cycle.

To make DC sync clock 3 times faster, I'm planning to change it here.

   rounded_pixel_clk = clk_round_rate(ipu->pixel_clk[disp], pixel_clk);      
   dev_dbg(ipu->dev, "round pixel clk:%d\n", rounded_pixel_clk);      
   ret = clk_set_rate(ipu->pixel_clk[disp], rounded_pixel_clk);      
   if (ret) 
   {
        dev_err(ipu->dev, "set pixel clk rate error:%d\n", ret);          
        return ret;      
   }      
   msleep(5);      /* Get integer portion of divider */     
   div = clk_get_rate(clk_get_parent(ipu->pixel_clk_sel[disp])) / rounded_pixel_clk;      
   dev_dbg(ipu->dev, "div:%d\n", div);      
   if (!div) 
   { 
       dev_err(ipu->dev, "invalid pixel clk div = 0\n");           
       return -EINVAL;      
   }        
   mutex_lock(&ipu->mutex_lock);       
   _ipu_di_data_wave_config(ipu, disp, SYNC_WAVE, div - 1, div - 1);      
   _ipu_di_data_pin_config(ipu, disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);

To add additional maps I guess I can do it here

void _ipu_init_dc_mappings(struct ipu_soc *ipu)

What I don't understand is here: how to configure the template to fetch the same RGB24 pixel three times and use 3 different maps to generate three output samples.

Specifically I want to understand what those 4 lines of WROD/WROD/WRG/WROD are doing, especially what's the meaning of "5"?

/* Init template microcode */           
if (disp) {                
    if ((pixel_fmt == IPU_PIX_FMT_YUYV)
        || (pixel_fmt == IPU_PIX_FMT_UYVY)
        ||(pixel_fmt == IPU_PIX_FMT_YVYU) 
        || (pixel_fmt == IPU_PIX_FMT_VYUY)) {
        _ipu_dc_write_tmpl(ipu, 8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1);
        _ipu_dc_write_tmpl(ipu, 9, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
        /* configure user events according to DISP NUM */                     
        ipu_dc_write(ipu, (width - 1), DC_UGDE_3(disp));                
    }
    _ipu_dc_write_tmpl(ipu, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
    _ipu_dc_write_tmpl(ipu, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
    _ipu_dc_write_tmpl(ipu, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
    _ipu_dc_write_tmpl(ipu, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
} else {                
     if ((pixel_fmt == IPU_PIX_FMT_YUYV) 
         ||(pixel_fmt == IPU_PIX_FMT_UYVY) 
         ||(pixel_fmt == IPU_PIX_FMT_YVYU) 
         ||(pixel_fmt == IPU_PIX_FMT_VYUY)) {
         _ipu_dc_write_tmpl(ipu, 10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1);  
         _ipu_dc_write_tmpl(ipu, 11, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);        
         /* configure user events according to DISP NUM */ 
         _ipu_dc_write(ipu, width - 1, DC_UGDE_3(disp)); 
      } 
      _ipu_dc_write_tmpl(ipu, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
      _ipu_dc_write_tmpl(ipu, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
      _ipu_dc_write_tmpl(ipu, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
      _ipu_dc_write_tmpl(ipu, 12, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
}

Re: Questions on IPU/DC configuration for 8 bit parallel display bus

igorpadykov — Wed, 04 May 2016 01:51:41 GMT

Hi Dehuan

WROD/WRG are described in sect.37.4.7.4.1 DC template's memory map

i.MX6DQ Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

it may be helpful to look at some examples with IPU microcode

i.MX53: How to move VGA external HSYNC and VSYNC signals to different pins?

Best regards

igor

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Questions on IPU/DC configuration for 8 bit parallel display bus

Re: Questions on IPU/DC configuration for 8 bit parallel display bus