i.MX Processors中的主题 Re: i.MX6SDL IDMAC setting for de-interlacing.

i.MX6SDL IDMAC setting for de-interlacing.

satoshishimoda — Fri, 18 Dec 2015 07:04:32 GMT

Hi community,

Our partner have a question about i.MX6S IPU IDMAC.

They want to use VDIC de-interlacing processing, but it has not worked well.

Then, we are checking IDMAC setting.

[Q1]

Please see Table 38-29 in IMX6SDLRM Rev.2.

For de-interlacing, IDMAC_CH_5, 9, 10, and 13 should be enabled.

Next, please see Table 38-9, ch 8 seems to be also needed not only ch 5, 9, 10, and 13.

Should we enabled ch 8 also?

[Q2]

Actually, ch 0 in Table 38-9 is enabled now.

To use VDIC de-interlacing, should we disable ch 0 to prevent collision?

Or we can ignore it?

Best Regards,

Satoshi Shimoda

Re: i.MX6SDL IDMAC setting for de-interlacing.

joanxie — Fri, 25 Dec 2015 08:04:29 GMT

Pls refer to the Table 38-30. IPU's Processing flows:

Interlaced input coming from the memory via 3 channels 8, 9 and 10.

so channel 8 is useful. for more detailed information, you can refer to this table ,and you can refer to the source code in the unit test, name includs "tvin".

Re: i.MX6SDL IDMAC setting for de-interlacing.

satoshishimoda — Mon, 28 Dec 2015 06:00:52 GMT

HI Guanqiong Xie,

Thank you for your reply, and sorry my information for your was not sufficient.

Our partner is using CSI -> VDIC -> Mem path with the setting written in the following post.

i.MX6 CSI -> VDIC path

According to your reply, channel 8 is useful for Mem -> VDIC -> Mem path.

But it is not useful for CSI -> VDIC -> Mem path since Table 38-29 does not mention channel 8, right?

Best Regards,

Satoshi Shimoda