<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックMIPI CSI-2 capabilities vs data lanes</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI-2-capabilities-vs-data-lanes/m-p/495413#M79692</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;About the MIPI CSI-2 capabilities, I would like to confirm if the following calculation is correct: for 1920 x 1080 @ 30 fps in video mode, do I need at least 3 data lanes?&lt;/P&gt;&lt;P&gt;F = 1920 * 1080 * 30 * 1.35 * 2 (cycles per pixel) = 168MHz&lt;/P&gt;&lt;P&gt;According to i.MX6QRM Rev. 2 page 2733, maximum bandwith for 2 lanes is 125MHz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 22 Mar 2016 14:18:13 GMT</pubDate>
    <dc:creator>g_moreno</dc:creator>
    <dc:date>2016-03-22T14:18:13Z</dc:date>
    <item>
      <title>MIPI CSI-2 capabilities vs data lanes</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI-2-capabilities-vs-data-lanes/m-p/495413#M79692</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;About the MIPI CSI-2 capabilities, I would like to confirm if the following calculation is correct: for 1920 x 1080 @ 30 fps in video mode, do I need at least 3 data lanes?&lt;/P&gt;&lt;P&gt;F = 1920 * 1080 * 30 * 1.35 * 2 (cycles per pixel) = 168MHz&lt;/P&gt;&lt;P&gt;According to i.MX6QRM Rev. 2 page 2733, maximum bandwith for 2 lanes is 125MHz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 22 Mar 2016 14:18:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI-2-capabilities-vs-data-lanes/m-p/495413#M79692</guid>
      <dc:creator>g_moreno</dc:creator>
      <dc:date>2016-03-22T14:18:13Z</dc:date>
    </item>
    <item>
      <title>Re: MIPI CSI-2 capabilities vs data lanes</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI-2-capabilities-vs-data-lanes/m-p/495414#M79693</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Guillermo&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I believe your calculations are correct, 3 data lanes are needed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Mar 2016 00:30:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI-2-capabilities-vs-data-lanes/m-p/495414#M79693</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-03-23T00:30:38Z</dc:date>
    </item>
    <item>
      <title>Re: MIPI CSI-2 capabilities vs data lanes</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI-2-capabilities-vs-data-lanes/m-p/495415#M79694</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you Igor.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Mar 2016 01:34:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MIPI-CSI-2-capabilities-vs-data-lanes/m-p/495415#M79694</guid>
      <dc:creator>g_moreno</dc:creator>
      <dc:date>2016-03-29T01:34:03Z</dc:date>
    </item>
  </channel>
</rss>

